46results about How to "Avoid programming" patented technology

In a memory with block management system, program failure in a block during a time-critical memory operation is handled by continuing the programming operation in a breakout block. Later, at a less critical time, the data recorded in the failed block prior to the interruption is transferred to another block, which could also be the breakout block. The failed block can then be discarded. In this way, when a defective block is encountered during programming, it can be handled without loss of data and without exceeding a specified time limit by having to transfer the stored data in the defective block on the spot. This error handling is especially critical for a garbage collection operation so that the entire operation need not be repeated on a fresh block during a critical time. Subsequently, at an opportune time, the data from the defective block can be salvaged by relocation to another block.

A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, the storage elements of a NAND string are partitioned into at least two regions. A first boosting voltage is applied to the first region of the string while a second larger boosting voltage is applied to the second region. The first region includes the addressed row or selected word line for programming. The boosting voltages are applied to the NAND strings of a block while the NAND strings are being inhibited from programming. In this manner, the second boosting voltage can be made larger without inducing program disturb on the memory cells receiving the larger boosting voltage. The boosted voltage potentials of the NAND string channels are trapped within the first region by lowering the boosting voltage on one or more bounding rows. The second boosting voltage is then lowered and data is applied to the bit lines of the NAND strings to select the appropriate strings for programming. The trapped voltage potential discharges or remains in the boosted state for programming depending on whether a string is selected for programming or is to remain inhibited from programming.

Programming NAND strings in a 3D stacked storage device to a conductive state. Storage elements may be erased by raising their Vt and programmed by lowering their Vt. Programming may include applying a series of increasing voltages to selected bit lines until the selected memory cell is programmed. Unselected bit lines may be held at about ground, or close to ground. The selected word line may be grounded, or be held close to ground. Unselected word lines between the selected word line and the bit line may receive about the selected bit line voltage. Unselected word lines between the source line and the selected word line may receive about half the selected bit line voltage. Programming may be achieved without boosting channels of unselected NAND strings to inhibit them from programming. Therefore, program disturb associated with leakage of boosted channel potential may be avoided.

A graphical user interface, implemented in a standard system management environment, accepts selections of logical instruction steps that are external to the standard system management environment. The logical instruction steps may include process steps, specify chemical formulae, or identify other components of master recipes that control drug manufacture or dispensing, as examples. The external logical instruction steps are introduced into the standard system management environment and approved. The standard system management environment subsequently controls the drug manufacturing or dispensing processes according to the external logical instruction steps.

A non-volatile memory device, which includes a plurality of memory transistors that are coupled with a plurality of bit lines and a plurality of word lines, and methods of operating a non-volatile memory device are provided. A selected bit line for programming and unselected bit lines for preventing programming are determined from the plurality of bit lines. An inhibiting voltage is applied to at least one inhibiting word line chosen from the plurality of word lines. The at least one inhibiting word line includes a word line positioned closest to a string selection line. A programming voltage is applied to a selected word line chosen from the plurality of word lines. Data is programmed into a memory transistor coupled with the selected word line and the selected bit line while preventing data from being programming into memory transistors coupled with the unselected bit line.

A memory device comprises a drain select line, a source select line, word lines, and a string connected between a bit line and a common source line. A program-inhibited voltage is applied to the bit line and a first voltage of a positive potential is applied to the drain select line. A second voltage for activating a programmed memory cell is applied to a word line to which the programmed memory cell is connected. A programming operation is performed by applying a program voltage to a selected word line and applying a pass voltage to the unselected word lines.

A nonvolatile memory cell (1) can be integrated in space-saving fashion into a semiconductor circuit (10) intended for volatile storage with the aid of volatile memory cells (2). The memory cell (1) has a programmable component (3) having an electrical resistance that can be altered by reprogramming, and also first (8) and second switching elements (9), which switch a first current path (J1) or a second current path (J2) in conducting fashion upon activation of optionally a first (11) or a second word line (12). At least one of the two current paths leads via the programmable component (3). Potentials of two bit lines (21, 22) to which the memory cell (1) according to the invention is connected can be altered as a result of the first or the second current path (J1, J2) being activated temporarily. The memory cell (1) permanently stores an item of digital information and can be driven by word lines (11, 12) and bit lines (21, 22) such as are conventionally used in volatile semiconductor memories (10). The invention opens up the possibility of integrating volatile and nonvolatile memory cells into a common memory cell array.

A data storage device may include a memory die. The memory die includes a memory and a latch. A method may include receiving a command corresponding to a write operation to write information to the memory. The method may further include loading a set of bits into the latch prior to receiving the information at the memory die. The set of bits includes at least a first bit having a first value and a second bit having a second value that is different than the first value. The method further includes receiving the information at the memory die and overwriting at least a portion of the set of bits at the latch with the information.

Embodiments of addressing the programming disturb effect are shown. A medium voltage having a magnitude between the programming voltage and ground is applied to a metal bit line among the cells that are subject to the program disturb effect.

An eFuse data alignment verification apparatus and method are provided. Alignment latches are provided in a series of latch units of a write scan chain and a logic unit is coupled to the alignment latches. A sequence of data that is scanned-into the series of latch units of the write scan chain preferably includes alignment data values. These alignment data values are placed in positions within the sequence of data that, if the sequence of data is properly scanned-into the series of latch units, cause the data values to be stored in the alignment latches. The logic unit receives data signals from the alignment latches and determines if the proper pattern of data values is stored in the alignment latches. If the proper pattern of data values is present in the alignment latches, then the data is aligned and a program enable signal is sent to the bank of eFuses.

A nonvolatile memory cell (1) can be integrated in space-saving fashion into a semiconductor circuit (10) intended for volatile storage with the aid of volatile memory cells (2). The memory cell (1) has a programmable component (3) having an electrical resistance that can be altered by reprogramming, and also first (8) and second switching elements (9), which switch a first current path (J1) or a second current path (J2) in conducting fashion upon activation of optionally a first (11) or a second word line (12). At least one of the two current paths leads via the programmable component (3). Potentials of two bit lines (21, 22) to which the memory cell (1) according to the invention is connected can be altered as a result of the first or the second current path (J1, J2) being activated temporarily. The memory cell (1) permanently stores an item of digital information and can be driven by word lines (11, 12) and bit lines (21, 22) such as are conventionally used in volatile semiconductor memories (10). The invention opens up the possibility of integrating volatile and nonvolatile memory cells into a common memory cell array.

The invention discloses a tensor-based land utilization simulation method, system and device and a storage medium. The method comprises the steps of obtaining land utilization data, driving factor data, a conversion cost table and an inertia intensity table; training a convolutional neural network to obtain a fitting model, and further obtaining a conversion probability tensor; executing neighborhood influence calculation to obtain a neighborhood influence tensor; executing conversion cost calculation to obtain a conversion cost tensor; executing inertia coefficient calculation to obtain an inertia coefficient tensor; obtaining a combined probability tensor according to the conversion probability tensor, the neighborhood influence tensor, the conversion cost tensor and the inertia coefficient tensor; and executing tensor wheel disc selection on the combined probability tensor to obtain a simulation result. According to the method, each part in the land utilization simulation process based on the cellular automaton is formalized into the tensor, and the tensor framework is applied to accelerate the operation, so that the efficient land utilization simulation process is realized while the complex parallel algorithm design and CUDA programming are avoided.

An eFuse data alignment verification apparatus and method are provided. Alignment latches are provided in a series of latch units of a write scan chain and a logic unit is coupled to the alignment latches. A sequence of data that is scanned-into the series of latch units of the write scan chain preferably includes alignment data values. These alignment data values are placed in positions within the sequence of data that, if the sequence of data is properly scanned-into the series of latch units, cause the data values to be stored in the alignment latches. The logic unit receives data signals from the alignment latches and determines if the proper pattern of data values is stored in the alignment latches. If the proper pattern of data values is present in the alignment latches, then the data is aligned and a program enable signal is sent to the bank of eFuses.

A method and system is disclosed for prohibiting program disturbance in a memory array device. The system comprises a bit-line decoder coupled to each bit-line of the memory array for providing a predetermined current diverting path, a biased resistance module placed on the bit-line of the flash memory array through which a pull-up current provided by a predetermined power supply is diverted by the bit-line decoder when a cell of the flash memory array connecting to the bit-line is programmed. The programming current of the cell of the flash memory array is stabilized due to the diverted pull-up current. This invention can reduce variance of programming current by the bit-line decoder diverted pull-up current, so can obtain more exact programming current to get preferable productivity, and this mechanism can be used for upgrading bit-line.

The invention relates to the field of biological information, and discloses a visual biological information analysis process framework system which comprises an application module and a process module. A plurality of configured biological information applications and software capable of meeting basic conventional analysis requirements of biological information analysis are arranged in the system,direct use of a user is supported, the process is visualized, the user can analyze the biological information more visually, meanwhile, and the system supports custom configuration of the applicationsand the process. A user can configure applications for the first time and then use the applications in multiple processes, the processes can automatically drag the corresponding applications according to requirements, the personalized analysis requirements of the user are met, various biological information analysis scenes can be applied, and the processes are configured in a'drag connection 'mode in the user-defined processes. Operation in the aspect of computer programming is avoided while the process is visualized, the difficulty of biological information analysis is reduced, and the analysis efficiency is improved.

The application provides a terminal, a server side and an instant messaging method and system. The method comprises the following steps: S1, receiving a webpage access request of a user; S2, loading a JS (JavaScript) script and executing the JS script; S3, constructing current information of the user into an original data packet through the JS script; S4, establishing a connection in an ajax way through the JS script, and transmitting the original data packet to the server side; S5, receiving a returned data packet transmitted by the server side through the JS script; S6, calling a callback function through the JS script in order to process and display the returned data packet; S7, judging whether the user inputs message information and requests transmission of the message information or not through the JS script, if not, executing the steps S3 to S7 repeatedly at an interval of 1 second, and if so, executing a step S8 and then executing the steps S4 to S7; and S8, constructing the current information of the user and the message information through the JS script to obtain the original data packet. The terminal, the server side and the instant messaging method and system are higher in mobility, do not occupy excessive server side resources, and can contribute to lowering of development cost.