The invention discloses an NAND Flash-based
data recording method and an NAND Flash-based
data recording controller. The method comprises the following methods: a hardware bad block management method comprising the following steps of: when a sudden bad block appears,
jumping to a next matched valid block without time
delay to continuously
record, and finally writing the data
lag of a page before the bad block appears back to the jumped valid block; a hardware balance method comprising the following step of: starting the erasing-writing operation in succession to the last erasing-writing address so that the erasing-writing times of each block of the NAND Flash is approximately equal; and an
input output (IO) expansion method comprising the following steps of: converting data bit width and switching control signals so that a single NAND Flash driver can control multiple chips and multiple groups of NAND Flashes. The controller comprises a ferroelectric
random access memory (FRAM) controller, a top state controller, a loss
equalizer, an interface switching module, a pre-matching module, an address generating module, a register set, a
data verification module, a standard first in first out (FIFO) interface, a standard
static random access memory (SRAM) interface, a command control interface and the NAND Flash driver. The whole controller can be mounted on a processor
local bus (PLB) of an embedded processor, and
data conversion between a
control signal and a state
signal can be performed through the command control interface and an external module.