35 results about "Bipolar transistor biasing" patented technology

A symmetrical blocking transient voltage suppressing (TVS) circuit for suppressing a transient voltage includes an NPN transistor having a base electrically connected to a common source of two transistors whereby the base is tied to a terminal of a low potential in either a positive or a negative voltage transient. The two transistors are two substantially identical transistors for carrying out a substantially symmetrical bi-directional clamping a transient voltage. These two transistors further include a first and second MOSFET transistors having an electrically interconnected source. The first MOSFET transistor further includes a drain connected to a high potential terminal and a gate connected to the terminal of a low potential and the second MOSFET transistor further includes a drain connected to the terminal of a low potential terminal and a gate connected to the high potential terminal.

Many integrated circuits include a type of transistor known as a bipolar junction transistor, which has an emitter contact formed of polysilicon. Unfortunately, polysilicon has a relatively high electrical resistance that poses an obstacle to improving switching speed and current gain of bipolar transistors. Current fabrication techniques involve high temperature procedures that melt desirable low-resistance substitutes, such as aluminum, during fabrication. Accordingly, one embodiment of the invention provides an emitter contact structure that includes a polysilicon-carbide layer and a low-resistance aluminum, gold, or silver member to reduce emitter resistance. Moreover, to overcome manufacturing difficulties, the inventors employ a metal-substitution technique, which entails formation of a polysilicon emitter, and then substitution or cross-diffusion of metal for the polysilicon.

A bandgap reference source having a low offset voltage and a high PSRR comprises: a first P tunnel field-effect transistor (MP1), a second P tunnel field-effect transistor (MP2), a third P tunnel field-effect transistor (MP3), a fourth P tunnel field-effect transistor (MP4), a first resistor (R1), a second resistor (R2), a third resistor (R3), a first bipolar transistor (Q1), a second bipolar transistor (Q2) and a voltage feedback circuit (10). The bandgap reference source having a low offset voltage and a high PSRR reduces the influence of tunnel length adjustment effect among various current mirrors, ensures the accuracy of a current multiplication factor, and thus reduces the offset of the output voltage by using a two-layer current mirror structure and increasing offset resistance.

Integrated circuits (ICs) utilize bipolar transistors in electro-static discharge (ESD) protection circuits to shunt discharge currents during ESD events to protect the components in the ICs. Bipolar transistors are subject to non-uniform current crowding across the emitter-base junction during ESD events, which results in less protection for the IC components and degradation of the bipolar transistor. This invention comprises multiple contact islands (126) on the emitter (116) of a bipolar transistor, which act to spread current uniformly across the emitter-base junction. Also included in this invention is segmentation of the emitter diffused region to further improve current uniformity and biasing of the transistor. This invention can be combined with drift region ballasting or back-end ballasting to optimize an ESD protection circuit.

A complementary lateral bipolar SRAM device and method of operating. The device includes: a first set and second set of lateral bipolar transistors forming a respective first inverter device and second inverter device, the first and second inverter devices being cross-coupled for storing a logic state. In each said first and second set, a first bipolar transistor is an PNP type bipolar transistor, and a second bipolar transistor is an NPN type bipolar transistor, each said NPN type bipolar transistor having a base terminal, a first emitter terminal, a second emitter terminal, and a collector terminal. Emitter terminals of the PNP type transistors of each first and second inverter devices are electrically coupled together and receive a first applied wordline voltage. The first emitter terminals of each said NPN transistors of said first inverter and second inverter devices are electrically coupled together and receive a second applied voltage. The second emitter terminal of one NPN bipolar transistor of said first inverter is electrically coupled to a first bit line conductor, and the second emitter terminal of the NPN bipolar transistor of said second inverter device is electrically coupled to a second bit line.

The present disclosure relates to FET-bipolar transistor combinations. A transistor switching device is provided which exhibits relatively good voltage capability and relatively easy drive requirements to turn the device on and off. This reduces transient drive currents that can upset other components.

The invention relates to a real-time junction temperature measuring method for a bipolar transistor working in an amplification zone, and belongs to the field of semiconductor device test. A Vbe-T relation curve between an emitter junction voltage and a temperature when the bipolar transistor works in different collector junction voltage Vce and collector currents Ice conditions is measured, a function expression of a temperature adjusting curve is obtained by fitting, and an Ice-Vbe-T junction temperature library is constructed under the different collector junction voltage Vce conditions. When the transistor works in the amplification zone, the electrification condition, namely values of the collector junction voltage Vce and the collector current Ice, as well as the emitter junction voltage Vbe measured in real time is substituted into the function expression to obtain the junction temperature in the moment. According to the method, the temperature adjusting curve under different electrification conditions is obtained by fitting, the corresponding function expression is obtained, and the junction temperature in the moment can be obtained by substituting the emitter junction voltage Vbe measured in real time into the function expression; and the real-time junction temperature measuring method is scientific and reasonable, low in errors and high in efficiency.

Improved protection circuits are provided for use as voltage overload protection circuits, ESD protection circuits for RF input pins, and unit protection cells for distributed amplifiers. Preferably, the protection circuits include a positive threshold voltage trigger used to trigger a switch wherein the trigger includes a diode string in series with a resistor and the switch includes a bipolar transistor switch in series with a single reverse diode. Alternatively, the trigger includes a diode string in series with a single diode and a single resistor, and is used to trigger a Darlington pair transistor switch in series with a single reverse diode. In another embodiment, a Darlington pair transistor switch is triggered by a capacitor. In use with distributive amplifiers, the ESD protection circuits are preferably absorbed inside the artificial transmission lines of the distributed amplifier.