44results about How to "Reduce line width roughness" patented technology

To achieve the foregoing and in accordance with the purpose of the present invention a method for etching an etch layer disposed below an antireflective coating (ARC) layer below a patterned mask is provided. The ARC layer is opened, and features are etched into the etch layer through the patterned mask. The opening the ARC layer includes (1) providing an ARC opening gas comprising a halogen containing gas, COS, and an oxygen containing gas, (2) forming a plasma from the ARC opening gas to open the ARC layer, and (3) stopping providing the ARC opening gas to stop the plasma. The patterned mask may be a photoresist (PR) mask having a line-space pattern. COS in the ARC opening gas reduces line width roughness (LWR) of the patterned features of the etch layer.

A method for reducing line width roughness (LWR) of a feature in an etch layer below a patterned photoresist mask having mask features is provided. The method includes (a) non-etching plasma pre-etch treatment of the photoresist mask, and (b) etching of a feature in the etch layer through the pre-treated photoresist mask using an etching gas. The non-etching plasma pre-etch treatment includes (a1) providing a treatment gas containing H2 and COS, (a2) forming a plasma from the treatment gas, and (a3) stopping the treatment gas.

A method for forming a photoresist mask may comprise providing a ultra-violet (UV) producing gas to a vacuum chamber having a substrate, ionizing the UV producing gas to produce UV rays to irradiate the substrate, and etching features into the substrate through the photoresist mask.

A resist coating / developing apparatus includes: a resist film-forming unit configured to apply a resist onto a substrate to form thereon a resist film; a resist developing unit configured to develop the resist film after exposure to pattern the resist film; a solvent gas generator configured to generate a solvent gas containing a vapor of a solvent having a property of dissolving the resist film; a solvent gas conditioner connected to the solvent gas generator and configured to condition the solvent gas generated in the solvent gas generator; a processing chamber configured to house the substrate having thereon the resist film which has been developed and patterned in the resist developing unit, and connected to the solvent gas conditioner so that the solvent gas, which has been conditioned in the solvent gas conditioning section, is supplied to the substrate housed in the processing chamber; and an exhaust system connected to the processing chamber to evacuate the processing chamber to a reduced pressure.

The present invention discloses a method of fabricating a semiconductor device. In the present invention, after the formation of a photo-resist mask on a substrate, the photo-resist is subjected to a plasma pre-treatment, and then etch is conducted. With the plasma pre-treatment, a line width roughness of a linear pattern of the photo-resist can be improved, and thus much better linear patterns can be formed on the substrate during the subsequent etching steps.

A formation method of a semiconductor structure is disclosed. The method comprises the following steps of providing a surface possessing a grid film substrate, wherein a grid pattern film including a hard mask layer material layer and a silicon material layer covers a grid film surface; forming a pattern layer on a grid pattern film surface; taking the pattern layer as a mask layer and etching a part of the grid pattern film to form a grid pattern layer, wherein the grid pattern layer comprises a hard mask layer and a silicon layer located on a hard mask layer surface; and a sidewall surface of the silicon layer, which is vertical to a first direction, possesses first line width roughness; carrying out repairing etching processing on the silicon layer sidewall vertical to the first direction so that the silicon layer sidewall surface possesses second line width roughness less than the first line width roughness; taking the grid pattern layer as the mask layer to etch a grid film and forming a grid on a substrate surface; and forming a source area and a leakage area in the substrate of two sides of a grid sidewall vertical to the first direction. By using the method, the line width roughness of the grid pattern layer is reduced so that formed grid quality is increased and electric performance of the semiconductor structure is optimized.

The invention relates to biphenyl molecular glass and a preparation method thereof, namely preparation of 2, 2' 1 2 (3, 5-di-tert-butyl-di-carbonate)-4, 4'-1 2 (di-tert-butyl-di-carbonate) biphenyl compound A and 2, 2', 4, 4'-4 (3, 5-di-tert-butyl-di-carbonate) biphenyl compound B. The diazotization reaction is conducted on 2, 2' 1 2 (3, 5-di-tert-butyl-di-carbonate)-4, 4'-benzidine under the condition of NaNO2 / H2SO4, then the 2, 2' 1 2 (3, 5-di-tert-butyl-di-carbonate)-4, 4'-benzidine is heated and hydrolyzed under the acidity condition, demethylation is conducted under the condition of BBr3 to obtain 2, 2' 1 2 (3, 5-dyhydroxy-phenyl)-4, 4'-diphenol, and finally the 2, 2' 1 2 (3, 5-dyhydroxy-phenyl)-4, 4'-diphenol reacts with (t-Boc)2O to obtain the compound A. The 2, 2' 1 2 (3, 5-di-tert-butyl-di-carbonate)-4, 4'-benzidine is diazotized and then mixed with potassium iodide to obtain 2, 2' 1 2 (3, 5-di-tert-butyl-di-carbonate)-4, 4'-biphenyl-diiodine. The 2, 2' 1 2 (3, 5-di-tert-butyl-di-carbonate)-4, 4'-biphenyl-diiodine conducts Suzuki reaction with 3, 5-dimethoxy benzene boric acid under catalyst of Pd(Ph3)4 / K2CO3 to obtain 2, 2', 4, 4'-4(3, 5-dimethoxy) biphenyl. 2, 2', 4, 4'-4(3, 5-dyhydroxy-biphenyl) is obtained by demethylation through the BBr3 under low temperature and reacts with the (t-Boc)2O to obtain the compound B.