54results about How to "Increase design complexity" patented technology

A register file backup system for use with a computer which processes instructions to generate results which thereby change the visual state of the computer. The computer has a register file with a plurality of addressable locations for storing data. The backup system is adapted to return the visual state of the computer to a previous state if an instruction generates an exception. The backup system utilizes less overhead so as to provide easier register file backup than a comparable software or hardware device. The backup system comprises first means for sequentially storing in program order, address information corresponding to destination locations in the register file where instruction results are to be stored. The first means has first and second outputs for transferring the address information stored therein: the first output being coupled to the register file for transferring a first portion of the address information to the register file, and the second output is used for transferring a second portion of address information for backup storage of the register file contents. The backup system also has a second means coupled to (1) the second output of the first means, for receiving and storing the second portion of the address information, and (2) the register file, for receiving and backup storing further information corresponding to the contents of one or more destination locations in the register file before that destination location is changed according to second portion of the address information. A third means is used for transferring the further information from the second means back to the register file locations according to the second portion of the address information stored in the second means after an instruction generates an exception.

A trench MOSFET device comprises: a substrate 200 of a first conductivity type, an epitaxial layer of the first conductivity type wherein the epitaxial layer has a lower impurity concentration than the substrate, a trench extending into the epitaxial layer, an insulated conductive region 211 within the trench, a doped region 206 of the first conductivity type formed within the epitaxial layer between a bottom portion of the trench and the substrate, wherein the doped region has an impurity concentration that is lower than that of the substrate and higher than that of the epitaxial layer, a body region 204 of a second conductivity type formed within an upper portion of the epitaxial layer and adjacent trench wherein the body region extends to a lesser depth from the upper surface of the epitaxial layer than does the trench and a source region 212 within the body region.

The invention discloses a human-machine interaction mode combing voice information with gesture information and an implementation device thereof. The human-machine interaction mode simultaneously uses the voice information and the gesture information to express a complicated control instruction so as to realize human-machine interaction in one-time interaction process. The device includes a camera, a voice sensor, and an image and voice processing system. With the specific scene description extracted from the gesture information, the complicated human-machine interaction control via voice can be carried out accurately, the communication efficiency of the human-machine interaction is greatly improved, and the user experience is improved. The human-machine interaction mode combing the voice information with the gesture information has the advantages of high accuracy and low complexity compared with other modes, and can be applied to devices having voice and image sensors conveniently.

The invention discloses a single-stage isolated PFC (power factor correction) converter direct-current control system and control method based on a DAB (dual active bridge). The original edge whole bridge inside phase shift ratio, the secondary edge whole bridge inside phase shift ratio and the phase shift ratio between original secondary edges of a DAB converter are coordinated, an additional current controller is omitted when inputted current is controlled, sine inputted current can be achieved by directly coordinating an outputted voltage controller, inputted voltage and current modulation,so that the cost of the system and the design difficulty of the controller are reduced, the stability of the control system is improved, and dynamic performance is improved.

Electronic device comprising an integrated circuit (1) embedded into a substrate, wherein the substrate has at least a first (3) and a second (9) conductive structure arranged on opposite sides of the integrated circuit (1) and the electrical connections (10,11,12,13) between the first (3) and the second (9) conductive structure and / or with the integrated circuit 5 (1) are established by means of holes (8) in the substrate.

A pitch control mechanism for an open rotor gas turbine engine is provided, the engine having a first rotor assembly and a second rotor assembly, with a plurality of airfoil blades circumferentially mounted on each rotor assembly, and arranged in contra-rotational relationship to each other. The pitch control mechanism includes an actuator assembly configured to be secured to a non-rotating frame of the engine, the actuator assembly having a first actuator and a second actuator, with the actuator assembly being rotationally isolatable from and couplable to the first and second rotor assemblies such that, in use, an actuation signal from the first or second actuator induces a corresponding desired change in pitch of the airfoil blades of the respective first or second rotor assembly independently of the pitch of the airfoil blades of the second or first rotor assembly.

The invention discloses a microprocessor data flow address matching self-trapping device. The microprocessor data flow address matching self-trapping device comprises a set of data flow address matching control registers with configurable software, data flow address matching judgment logic, data flow address matching self-trapping generation logic of precise interrupts and microprocessor operating state storage logic, wherein if a data flow address meets specified requirements of the data flow address matching control registers, data flow address self-trapping of the precise interrupts is generated, and a processor can reserve an operating state, and not only facilitates program debugging for a user, but also provides powerful support for operating system debugging. The microprocessor data flow address matching self-trapping device supports software in a specified matching pattern (equal match or unequal match), specifying the type of 'an address to be matched'(a virtual address or a physical address) and specifying the bit width of 'the address to be matched'(a full address or a partial address), and means of software debugging are richened. According to the microprocessor data flow address matching self-trapping device, existing access and storage hardware logic is effectively used for achieving the function, and hardware design complexity and hardware cost need not to be increased obviously.

In some embodiments, a register file circuit design process includes instructing an automated integrated circuit design program to generate a register file circuit design, including providing a cell circuit design and instructing the automated integrated circuit design program to generate a selection design, a pre-decode design, and a data gating design. The cell circuit design describes a plurality of selection circuits that have a particular arrangement. The selection design describes a plurality of replica circuits that include respective pluralities of selection circuits having the particular arrangement. The pre-decode design describes a pre-decode circuit configured to identify a plurality of entries identified by a portion of a write instruction. The data gating design describes data gating circuits configured, in response to the pre-decode circuit not identifying respective entries, to disable data inputs to respective write selection circuits connected to the respective entries.