71results about How to "Improve electrical quality" patented technology

A contact pin for an electrical connector comprises a body, a connector element, and a sheath, the connector element being maintained in the extension of the body by being coupled with a peg projecting from the front face of the body, the sheath being disposed around the connector element and maintained on the body by clamping an annular portion of the latter. At the peg end, connector element comprises an end for coupling with said pin, conformed such that the pin cannot fit inside the cross section of said coupling end, the connector element being capable of deforming elastically to enable its coupling end to friction fit onto the pin, the thus deformed connector element being unable to fit inside the cross section of the sheath.

The invention provides a power switching device for network equipment to switch the power of Ethernet (POE) or DC power supply to supply power to loads in the network equipment. The power switching device comprises a first input end into for a first wire head to be inserted, a second input end for a second wire head to be inserted, an output end for outputting output voltage, and a switching circuit connected with the first input end, the second input end and the output end, wherein the switching circuit is inserted into the second input end through the second wire head to cut off output voltage supplied by the first wire head and uses the second wire head to supply output voltage.

The inventions presented herein provide a electronically controlled phase shifters that incorporate analog and digital phase shift architectures in a novel manner that realizes the best advantages of each architecture. This combination of complementary phase shift architectures provides the high-performance and low loss characteristics of switched digital phase shift architectures with the high resolution and precision of continuous analog phase shift architectures. The circuit embodiments are electronically controlled, which simplifies implementation of what is a complex circuit. The analog phase shift elements comprise electronically-tuned varactors, which provide fine resolution and enables the incorporation of active compensation for manufacturing variation before use or for environmental conditions during use.

A chip package structure including a substrate, at least one chip, a heat dissipation device, at least one first conductive bar, a molding compound, and at least one second conductive bar is provided. The chip and the heat dissipation device are respectively disposed on a first and a second surface of the substrate. The first conductive bar has two opposite end surfaces, wherein one end surface is disposed on the first surface of the substrate, the other end surface is extended away from the substrate, and a fastening slot is disposed between the two end surfaces and passes through the other end surface. The molding compound encapsulates the substrate, the chip, part of the heat dissipation device, and the first conductive bar. The second conductive bar is disposed on one surface of the molding compound and has a protrusion portion fastened to the fastening slot of the first conductive bar.

The method includes the steps: 1) to from a insulating layer on a base board, 2) to form an amorphous silicon layer on the insulating, layer, the amorphous silicon layer includes a amorphous silicon thick area and a amorphous silicon thin area, 3) to fully melt the amorphous silicon layer to a first molten state amorphous silicon area that center of the bottom is corresponding to center of bottom of the amorphous silicon thick area and a second molten state amorphous silicon area that center of the bottom is corresponding to center of the amorphous silicon thin area. The temp. of first molten state amorphous silicon area is lower than the temp. of second molten state amorphous silicon area. Finally, to crystallize from first molten state amorphous silicon area to second molten state amorphous silicon area, thus to form polysilicon layer.

The invention relates to an integrated passive device wafer-level packaging three-dimensional stacked structure and a manufacturing method. The integrated passive device wafer-level packaging three-dimensional stacked structure comprises a wafer-level packaging chip and an IPD chip. The IPD chip comprises a glass substrate, wherein an IPD device and a metal wiring layer are arranged on the front surface of the glass substrate, the back surface of the glass substrate is etched to form TGV holes, back surface metal wiring layers are arranged on the back surface of the glass substrate and the inner surfaces of the TGV holes, a welding ball is arranged on a welding pad of each back surface metal wiring layer, and the welding balls are connected with a PCB. The manufacturing method of the three-dimensional stacked structure comprises the following steps that (1) the wafer-level packaging chip and the IPD chip of the glass substrate are stacked; (2) the back surface of the IPD chip is etched to form the TGV holes, the back surface metal wiring layer is manufactured on the back surface of the glass substrate; (3) the back surface metal wiring layer is etched into two insulated parts; the welding pads and welding balls are manufactured on the two parts of the back surface metal wiring layer, and the welding balls are connected with the PCB. By means of the integrated passive device wafer-level packaging three-dimensional stacked structure and the manufacturing method, short-distance interconnection between the chip and the IPD device is achieved, and the electric quality is improved.

The invention relates to a semiconductor packaging substrate and a fabricating method thereof. The invention is characterized in that electric connection pads on the surface of a circuit board provided with a wire bonding area and a lug area synchronously form a nickel/palladium/metal layer, so as to reduce the flow of process and the waste of time. The effect for enhancing the binding force between the substrate and the chip exists in the nickel/palladium/metal layer.

The invention relates to an electronic device, a thin-film transistor, a display device and conductor contact process. The electronic device is at least provided with a conductor pattern configured ona substrate. The conductor pattern comprises a substantive pure aluminum layer and an aluminum nickel lanthanide alloy layer, the substantive pure aluminum layer is configured on the substrate, and the aluminum nickel lanthanide alloy layer is configured on the substantive pure aluminum layer. The electronic device has the advantages of low manufacturing cost, good electrical property and good manufacturing yield.

A package substrate including a fine redistribution circuitry, a first redistribution circuitry disposed on the fine redistribution circuitry and a core disposed on the first redistribution circuitry opposite to the fine redistribution circuitry. The fine redistribution circuitry includes a fine conductive pattern. The first redistribution circuitry includes a first conductive pattern electrically connected to the fine conductive pattern. A thickness of the fine redistribution circuitry is less than a thickness of the first redistribution circuitry and a dimension of the fine conductive pattern is less than a dimension of the first conductive pattern. The core is electrically connected to the first conductive pattern. The Young's modulus of the core is greater than the Young's modulus of the first redistribution circuitry. A package structure is also provided.

A fabricating process of a circuit board with an embedded passive component is described. First, a conductive layer including a first surface and a second surface opposite thereto is provided. The first surface has at least one component region on which at least one passive component material layer is formed. A passivation layer is formed on the first surface to cover the passive component material layer. A brown oxidation process is performed on the conductive layer. A circuit unit and an insulation layer are provided, and the insulation layer is set between the circuit unit and the conductive layer. The conductive layer, the circuit unit and the insulation layer are laminated. The passive component material layer is between the insulation layer and the conductive layer. The conductive layer is patterned to form a circuit layer.

The invention provides a manufacturing method of a thin film transistor. A method for forming a back channel comprises the following steps: S21, laminating and manufacturing an active material film, asource and drain electrode material film and a photoresist material film on a gate insulation layer so as to obtain an etched substrate; S22, carrying out primary wet etching, primary dry etching andphotoresist burning and secondary wet etching on the etched substrate in sequence so as to form a source electrode, a drain electrode and a photoresist layer; S23, etching the active material film byadopting a first etching gas so as to form the back channel; and S24, removing the photoresist layer by adopting a second etching gas so as to obtain the thin film transistor. According to the manufacturing method, a copper stripping solution can be avoided from being used when the back channel is etched, and the compositions and using amounts of various etching gases are reasonably matched, so that the problems of copper ion diffusion and pollution of other impurity ions in the copper stripping solution in the prior art are further avoided while back channel etching and photoresist removal are completed. The invention also provides application of the manufacturing method in an array substrate.

A manufacturing method of a circuit structure is provided. A metal layer having an upper surface is provided. A surface passivation layer is formed on the metal layer. The surface passivation layer exposes a portion of the upper surface of the metal layer, and a material of the metal layer is different from a material of the surface passivation layer. The metal layer and the surface passivation layer are dipped into a modifier, and the modifier is selectively absorbed and attached to the surface passivation layer, so as to form a covering layer. The covering layer has a plurality of nanoparticles and covers the surface passivation layer.