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37results about How to "Eliminate bias effects" patented technology

Semiconductor device and method of producing same

A semiconductor device suitable for a source-follower circuit, provided with a gate electrode formed on a semiconductor substrate via a gate insulation film, a first conductivity type layer formed in the semiconductor substrate under a conductive portion of the gate electrode and containing a first conductivity type impurity, first source / drain regions of the first conductivity type impurity formed in the semiconductor substrate and extended from edge portions of the gate electrode, and second source / drain regions having a first conductivity type impurity concentration lower than that in the first source / drain regions and formed adjoining the gate insulation film and the first source / drain regions in the semiconductor substrate so as to overlap portions of the conductive portion of the gate electrode.
Owner:SONY SEMICON SOLUTIONS CORP

Displacement register capable of reducing voltage bias effective voltage

ActiveCN101042937AReduce bias effectsIncreased steady state timeStatic indicating devicesDigital storageVoltageShift register
This invention discloses one displacement register, which comprises one first frequency signal pull down module, one second frequency signal pull down module, one first main pull down module, one second pull down module and one discharge circuit, wherein, when the first and second pull down modules generate abnormal circuit to make the register not capable of discharge, the discharge circuit can proceed to lower the register circuit bias effect.
Owner:AU OPTRONICS CORP

Method for teeth model parameterization

The invention discloses a method for teeth model parameterization. The method comprises the steps of calculating geometric center points of all teeth; fitting an upper jaw dentofacial plane and a lower jaw dentofacial plane, and calculating an upper jaw dental arch curve and a lower jaw dental arch curve; determining tip points of canine teeth of the upper jaw and the lower jaw; determining far-near-middle points, near-middle points and far-middle points of the teeth; determining a teeth coordinate system according to the tip points, the far-near-middle points, the near-middle points and the far-middle points; calculating FA points, central points and cutting edge points of the teeth, and the near-far-middle cheek points of accessional teeth; performing lip cheek-direction adjustment, tongue jaw-direction adjustment, single-tooth characteristic point adjustment and original tooth die long-axis adjustment; arranging the teeth at a single jaw according to a tooth position number sequencefrom incisor teeth along a dental arch through using the middle line of the dental arch as a reference; calculating a collision value between the single tooth and the adjacent tooth with a relativelysmall tooth position number, and moving a near-middle edge point according to the collision value. The method of the invention effectively improves accuracy and rationality of the parameters after teeth model parameterization.
Owner:INNOVATIVE MATERIAL & DEVICES

Charge pump circuit of charge transfer structure suitable for low-voltage operation

The invention relates to a charge pump circuit of a charge transfer structure CTS suitable for low-voltage operation. The charge pump circuit comprises a plurality of cascaded CTS charge pump sub-units. Each stage of CTS charge pump sub-unit comprises the components of a first NMOS transistor as a transmission switch, the drain electrode of the first NMOS transistor is connected with the input end of this stage, and the source electrode is connected with the output end of this stage; a second NMOS transistor of which the drain electrode is connected with the input end of this stage, the source electrode is connected with the gate electrode of the first NMOS transistor, and the gate electrode is connected with the output end of this stage; a PMOS transistor of which the source electrode is connected with the gate electrode of the first NMOS transistor, the drain electrode is connected with the output end of a next stage, and the gate electrode is connected with the output end of this stage; and a random phase clock signal in a pair of phase clock signals, wherein the random phase clock signal is transmitted to the output end of this stage through an energy storage lifting capacitor. The charge pump circuit is based on the improvement of the existing CTS charge pump sub-unit and a cascaded circuit, and increases the gate electrode voltage of the NMOS transistor as a transmission switch through a simpler structure. Furthermore the charge pump circuit has functions of reducing side effect of a substrate bias effect and simplifying design for a circuit board diagram.
Owner:GIANTEC SEMICON LTD

Semiconductor memory device

A semiconductor memory device is provided which has a hierarchical bit line structure and can perform a high-speed read operation even with a low voltage. A subarray 12 includes a first MOS transistor PD1 for charging a main bit line MBL1 and a second MOS transistor PS1 for charging a sub-bit line SBL1—1. The source electrode of the second MOS transistor PS1 is connected to a power source voltage, and the source electrode of the first MOS transistor PD1 is connected via a fourth MOS transistor PD2 to the power source voltage. Since there is not a resistance between the main bit line MBL1 and the sub-bit line SBL1—1, which is present if a transistor is used to achieve conduction therebetween, discharging of the main bit line and charging of the sub-bit line can be performed with high speed.
Owner:SOCIONEXT INC

Bias-free regularization for spectral phase-unwrapping in differential phase contrast imaging

Methods and related apparatus (SP) to correct phase shift image data for phase wrapping artifacts. The data is detected at a detector (D) of an imaging system (IM) including interferometric equipment (G0, G1, G2). In a phase unwrapping method that involves optimizing an objective function with regularization, a two-sage approach is proposed. The measured data is processed in one stage with regularization and in the other stage without regularization. This allows improving the accuracy of the corrected (phase unwrapped) phase shift data because an undesirable bias caused by the regularization can be avoided.
Owner:KONINKLJIJKE PHILIPS NV

Method for fabricating thin film transistors

InactiveUS20080254578A1Promote electric performanceIncrease uniformitySolid-state devicesSemiconductor/solid-state device manufacturingPhysicsLaser annealing
A method for fabricating thin film transistors is disclosed. An amorphous silicon film is formed on a substrated and selectively irradiated with a laser beam for lateral growth to form a plurality of polysilicon regions. The whole surface of the substrate is then oxidized and irradiated with exicer laser annealing.
Owner:CHUNGHWA PICTURE TUBES LTD

Chemical oxidation technology of gold film of porous ZM6 magnesium alloy spare part

The invention belongs to the field of surface treatment of a magnesium alloy spare part and particularly relates to a chemical oxidation technology of a gold film of a porous ZM6 magnesium alloy sparepart. The technology comprises the following steps: step I: preparing ZM6 magnesium alloy chemical oxidation tank liquor, step II: performing chemical oxidation, and step III: detecting dimensional precision of pores before and after the chemical oxidation. According to the technology, contents of ingredients of the tank liquor are adjusted; an acid mist inhibitor preventing volatilization of acetic acid during heating is added; the gold film can be obtained by oxidizing the porous ZM6 magnesium alloy spare part with a chemical oxidation solution formula; a film layer is uniform; the obtainedgold film layer is high in repeatability during testing; the influence on pore precision is small; and the influence of the surface treatment on the dimension and appearance of the porous magnesium alloy spare part is comprehensively reduced.
Owner:BEIJING XINGHANG MECHANICAL ELECTRICAL EQUIP

FPGA measuring unit and channel delay compensation method and device based on FPGA measuring unit

The invention provides an FPGA measuring unit and a channel delay compensation method and device based on the FPGA measuring unit. The measuring unit comprises a logic unit, a pulse signal sending unit and a plurality of input and output units, wherein the pulse signal sending unit and the input and output units are connected with the logic unit. Each input and output unit comprises a receiver, a delay adjustment module and a sampling register which are connected in sequence; the sampling register and the pulse signal sending unit are connected with the same system clock; the pulse signal sending unit is connected with a plurality of connection points in the tested equipment; the plurality of connection points are respectively connected with the plurality of receivers in a one-to-one correspondence manner; a complete path from one connection point to one sampling register is a channel; and the delay adjustment module is used for compensating delay deviation between the channels. According to the invention, the delay among multiple channels can be accurately compensated, so that the deviation influence of the measurement unit itself is eliminated, and the self-calibration of the measurement unit is completed.
Owner:HANGZHOU CHANGCHUAN TECH CO LTD
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