Charge pump circuit of charge transfer structure suitable for low-voltage operation

Abstract

The invention relates to a charge pump circuit of a charge transfer structure CTS suitable for low-voltage operation. The charge pump circuit comprises a plurality of cascaded CTS charge pump sub-units. Each stage of CTS charge pump sub-unit comprises the components of a first NMOS transistor as a transmission switch, the drain electrode of the first NMOS transistor is connected with the input end of this stage, and the source electrode is connected with the output end of this stage; a second NMOS transistor of which the drain electrode is connected with the input end of this stage, the source electrode is connected with the gate electrode of the first NMOS transistor, and the gate electrode is connected with the output end of this stage; a PMOS transistor of which the source electrode is connected with the gate electrode of the first NMOS transistor, the drain electrode is connected with the output end of a next stage, and the gate electrode is connected with the output end of this stage; and a random phase clock signal in a pair of phase clock signals, wherein the random phase clock signal is transmitted to the output end of this stage through an energy storage lifting capacitor. The charge pump circuit is based on the improvement of the existing CTS charge pump sub-unit and a cascaded circuit, and increases the gate electrode voltage of the NMOS transistor as a transmission switch through a simpler structure. Furthermore the charge pump circuit has functions of reducing side effect of a substrate bias effect and simplifying design for a circuit board diagram.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a charge pump circuit for generating high voltage in an EEPROM (Electrically Erasable Programmable Read-Only Memory, Electrically Erasable Programmable Read-Only Memory) or a flash memory chip. Background technique [0002] With the rise of handheld devices and the Internet of Things, the demand for integrated circuit miniaturization and energy-saving design is becoming more and more urgent, which puts forward requirements for the design of low power supply voltage of semiconductor integrated circuits. Because EEPROM and flash memory devices have the characteristics of flexible data rewriting, stored data content will not be lost after power failure, and can be kept for a long time, they are more and more widely used in the system. [0003] In CMOS EEPROM or flash memory devices, whether based on floating gate technology or charge trap technology, a high voltage generation ci...

AI Technical Summary

Problems solved by technology

M0 and M3 are used in parallel in the circuit and need to occupy a larger layout area

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