FPGA measuring unit and channel delay compensation method and device based on FPGA measuring unit

Abstract

The invention provides an FPGA measuring unit and a channel delay compensation method and device based on the FPGA measuring unit. The measuring unit comprises a logic unit, a pulse signal sending unit and a plurality of input and output units, wherein the pulse signal sending unit and the input and output units are connected with the logic unit. Each input and output unit comprises a receiver, a delay adjustment module and a sampling register which are connected in sequence; the sampling register and the pulse signal sending unit are connected with the same system clock; the pulse signal sending unit is connected with a plurality of connection points in the tested equipment; the plurality of connection points are respectively connected with the plurality of receivers in a one-to-one correspondence manner; a complete path from one connection point to one sampling register is a channel; and the delay adjustment module is used for compensating delay deviation between the channels. According to the invention, the delay among multiple channels can be accurately compensated, so that the deviation influence of the measurement unit itself is eliminated, and the self-calibration of the measurement unit is completed.

Description

technical field [0001] The present application relates to the field of software technology, in particular to an FPGA measurement unit and a channel delay compensation method and device based on the FPGA measurement unit. Background technique [0002] In ATE equipment, an external measurement unit or device is usually used to measure the time delay deviation of all signals (such as 256 channels) in each SLOT slot to the POGO device under test. In order to ensure measurement accuracy, the measurement unit itself must not introduce additional deviations . Delay deviations often exist between different channels in FPGA-based measurement units, including wiring delays, device delays, and sampling clock delays. In the prior art, in order to eliminate the deviation of the FPGA-based measurement unit itself, timing constraints are usually set inside the FPGA. Through this constraint, the internal routing of the FPGA is prioritized according to the set value. However, the constraint...

AI Technical Summary

Problems solved by technology

In the prior art, in order to eliminate the deviation of the FPGA-based measurement unit itself, timing constraints are usually set inside the FPGA. Through this constraint, the internal routing of the FPGA is prioritized according to the set value. However, the constraint accuracy of this method is low, usually within ns The order of magnitude cannot completely eliminate the deviation introduced by the measurement unit itself, so it cannot meet the requirements of high-speed, high-precision applications

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