42 results about "Emitter-coupled logic" patented technology

An ultra high speed Emitter Coupled Logic (ECL) flip-flop is provided and a method of operating the same. The ECL flip-flop provides for clock levels that operate at logic levels above the data levels. Since the clock operates at logic levels above the data, the clock experiences level shifts that are less than the level shifts of the data. Therefore, the clock will provide a higher fidelity signal relative to the conventional clock signal. The ECL flip-flop can operate at significantly higher data rates than conventional flip-flop circuitry.

A multiple signal format output driver is configurable to provide a current-mode logic (CML) output signal in response to a CML value of one or more first values of the control signal. The output driver is configurable to provide a low-power, low-voltage positive emitter-coupled logic (low-power LVPECL) output signal in response to a low-power LVPECL value of the one or more first values of the control signal. The output driver is configurable to provide a low-voltage differential signaling (LVDS) output signal in response to an LVDS value of the one or more first values of the control signal. The output driver may be configurable to provide a LVPECL output signal in response to a second value of the control signal. The output driver may be configurable to provide a high-speed current steering logic (HCSL) output in response to a third value of the control signal.

The invention provides a system for acquiring and distributing baseband data of a remote sensing satellite. The system comprises a task management device, a data acquiring device, a data storage device and a data distributing device. When detecting a data acquisition task list, the data acquiring device acquires baseband data of the remote sensing satellite and corresponding time code information thereof from the remote sensing satellite by a fully digital demodulator via the network. The data distributing device distributes the required baseband data of the remote sensing satellite to user equipment after receiving data distribution requests of the user equipment. By the aid of the system, the baseband data of the remote sensing satellite can be acquired in real time via the network, and meanwhile, uniform data distributing services can be provided to rear-end equipment via the network, and accordingly, limits of ECL (emitter-coupled logic) signal transmission distance and special acquisition cards are eliminated.

A clock down sensor mainly comprises a converter and a low-pass filter. The converter is used to convert an input signal from a PECL (Positive Emitter Coupling Logic) signal to a TTL (Transistor Transistor Logic) signal, the low pass filter is used to obtain a DC (Direct Current) level of the TTL signal. Thereby, the sensor can judge whether the clock signal is terminated according to the potential of the output signal in order to emit a warning so that a breakdown elimination inquiry can be done or automatic breakdown elimination can be processed earlier.

The invention discloses a programmable ECL (emitter coupled logic) device based a high-frequency phase shift signal generation circuit. The existing high-frequency signal generator is expensive and the hardware circuit is complex. The programmable ECL device based a high-frequency phase shift signal generation circuit provided by the invention comprises a rapid comparator, a PLL (phase locking loop) frequency multiplier, an ECL signal clock distributor, a pulse suppressor, a first digital frequency divider and a second digital frequency divider; the rapid comparator converts an external clock signal into a square wave signal; the PLL frequency multiplier performs frequency multiplying on the square wave signal; the ECL signal clock distributor distributes the frequency multiplying signal to two ways, one way of the frequency multiplying signal is directly subjected to frequency division through the first digital frequency divider, and the other way of frequency multiplying signal is subjected to frequency division by the second digital frequency divider after the pulse suppressor suppresses a phase shift of 2pi; the frequency dividing multiple of the first digital frequency divider and the second digital frequency divider is respectively 2, and the output signal of the first digital frequency divider has the phase shift as shown in the specification relative to the output signal of the second digital frequency divider. According to the invention, the circuit design principle is simple, and the duplicability is high.

The invention implements a Positive Emitter Coupled Logic (PECL) output using CMOS transistors that approximate the Motorola ECL characteristics into standard PECL termination schemes. By creating a PECL output using a switchable current source the PECL output can be integrated into a Low Voltage Differential Signaling (LVDS) structure. The invention allows the user to switch between PECL and LVDS outputs via control logic by enabling the specific circuit elements for each signaling technology. With this invention, the combination of two drivers on one IC device gives system designers the flexibility to use the same circuitry in two separate signaling schemes. Thus, the designers can select to use one output characteristics or the other for their designs.