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PECL (Positive Emitter Coupling Logic) level interface circuit

An interface circuit and level technology, applied in the direction of logic circuit connection/interface layout, etc., can solve the problems of unsatisfactory common mode level and large output impedance, and achieve the effects of high precision, high reliability and simple circuit structure.

Active Publication Date: 2011-06-08
XIAMEN UX HIGH SPEED IC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, for the CMOS process, limited to the characteristics of the voltage parameters corresponding to the process, if an open source circuit (Open Source) similar to the open emitter is used to construct the PECL level interface, the output impedance is relatively large, and the common mode level cannot be satisfied. Vcc-1.3, so the CMOS process cannot realize such a PECL output interface with a simple open source structure

Method used

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  • PECL (Positive Emitter Coupling Logic) level interface circuit
  • PECL (Positive Emitter Coupling Logic) level interface circuit
  • PECL (Positive Emitter Coupling Logic) level interface circuit

Examples

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Embodiment 1

[0039] figure 1 It is the equivalent schematic diagram of Dai Wenning defined by the PECL standard. For a differential load with an AC load impedance of 50Ω, the common-mode level of the output node is maintained at VCC-1.3V, and the differential output amplitude is about 1.4Vpp. Generally, it is implemented as figure 2 As shown, it is a PECL output circuit with a traditional open-emitter structure, and this structure is also the origin of the name of the PECL interface. The output impedance of the transistor with the open emitter structure is relatively low, and it works in an amplified state. Therefore, the circuit with this structure can meet the common-mode voltage requirement of Vcc-1.3V while driving various specific load forms. However, if such a structure is realized by CMOS technology, the gate, drain and source of the MOS are simply replaced with the base, collector and emitter of the transistor, even if the bias of the appropriate MOS transistor is used, the It c...

Embodiment 2

[0042] Figure 4It is the circuit diagram of the voltage generator in the common mode negative feedback module of the second embodiment of the present invention; the function of the voltage generator is to generate a Vcc-1.3V reference voltage following Vcc; the voltage generator adopts the reference voltage 1.2V under the CMOS process V is a reference reference, and then a constant current branch is formed by the comparator A1, the adjustment tube M0 and the resistor R0, and the reference reference flows through R0 to obtain a constant current, and the mirror current source including M1, M2, and M3 will This constant current is mirrored to R1, and finally Vref following Vcc is obtained from the low potential end of R1. The relationship between R0 and R1 is determined as: R1 / R0=1.3 / 1.2, then Vref=Vcc-1.3V can be obtained, and the Vref precision of this structure is higher.

[0043] Such as Figure 5 , the circuit diagram of the negative feedback driver in the common mode neg...

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Abstract

The invention discloses a PECL (Positive Emitter Coupling Logic) level interface circuit. The circuit is characterized by comprising a gain module, an output drive module and a common-mode negative feedback module, wherein an input CMOS (Complementary Metal-Oxide-Semiconductor) differential signal is received and amplified by the gain module, is transmitted to the output drive module through the differential signal output end, and is output from the PECL level output end of the output drive module; the input end of the common-mode negative feedback module is connected in parallel to the PECL level output end, and provides a negative feedback signal to the output drive module; and the output drive module and the negative feedback module commonly perform level modification on the amplified differential signal to ensure that the final signal output from the PECL level output end fulfills the PECL level with Vcc-1.3V common-mode voltage. The PECL level interface circuit provides the common-mode negative feedback mode by the common-mode negative feedback module, and performs common-mode voltage modification on the signal in the drive module to ensure that the circuit with the CMOS process can output a signal with PECL level standard.

Description

technical field [0001] The invention relates to a level conversion device, in particular to a PECL level interface circuit. Background technique [0002] PECL (Positive Emitter Coupling Logic), positive emitter coupling logic, is a high-speed circuit interface standard commonly used in optical fiber communication systems. In its standard definition, the common mode level of the driving signal is VCC-1.3V, and the AC load impedance It is a 50ohm differential load, and the differential output amplitude is about 1.4Vpp. [0003] The traditional PECL output circuit is implemented by an open emitter circuit (Open Emitter), which is the origin of the interface name. Since the open emitter structure has low output impedance, and the bipolar circuit uses current amplification characteristics, the structure circuit can meet the output common mode level of VCC-1.3 while satisfying various specific load forms. Require. [0004] However, for the CMOS process, limited to the character...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/0175
Inventor 林少衡
Owner XIAMEN UX HIGH SPEED IC
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