57results about How to "Strong Gap Filling Capability" patented technology

In one embodiment, a semiconductor substrate is placed into a process chamber. A gas mixture including a silicon-containing gas, a fluorine-containing gas, an inert gas, and an oxygen gas is introduced into the chamber at a pressure range of from about 30 mTorr to about 90 mTorr. During this time, deposition and etching processes are concurrently performed using a plasma to form a high-density plasma (HDP) insulating layer on the semiconductor substrate. A ratio of deposition to etching is from about 3:1 to about 10:1. A ratio of a flow rate of the fluorine-containing gas to a flow rate of the silicon-containing gas is less than about 0.9.

An apparatus for plating a conductive film directly on a substrate with a barrier layer on top includes anode rod (1) placed in tube (109), and anode rings (2), and (3) placed between cylindrical walls (107) and (105), (103) and (101), respectively. Anodes (1), (2), and (3) are powered by power supplies (13), (12), and (11), respectively. Electrolyte (34) is pumped by pump (33) to pass through filter (32) and reach inlets of liquid mass flow controllers (LMFCs) (21), (22), and (23). Then LMFCs (21), (22) and (23) deliver electrolyte at a set flow rate to sub-plating baths containing anodes (3), (2) and (1), respectively. After flowing through the gap between wafer (31) and the top of the cylindrical walls (101), (103), (105), (107) and (109), electrolyte flows back to tank (36) through spaces between cylindrical walls (100) and (101), (103) and (105), and (107) and (109), respectively. A pressure leak valve (38) is placed between the outlet of pump (33) and electrolyte tank (36) to leak electrolyte back to tank (36) when LMFCs (21), (22), (23) are closed. A wafer (31) held by wafer chuck (29) is connected to power supplies (11), (12) and (13). A drive mechanism (30) is used to rotate wafer (31) around the z axis, and oscillate the wafer in the x, y, and z directions shown. Filter (32) filters particles larger than 0.1 or 0.2 mum in order to obtain a low particle added plating process.

A method of depositing a silicon oxide layer over a substrate having a trench formed between adjacent raised surfaces. In one embodiment the silicon oxide layer is formed in a multistep process that includes depositing a first portion of layer over the substrate and within the trench by forming a high density plasma process that has simultaneous deposition and sputtering components from a first process gas comprising a silicon source, an oxygen source and helium and / or molecular hydrogen with highD / S ratio, for example, 10-20 and, thereafter, depositing a second portion of the silicon oxide layer over the substrate and within the trench by forming a high density plasma process that has simultaneous deposition and sputtering components from a second process gas comprising a silicon source, an oxygen source and molecular hydrogen with a lowerD / S ratio of, for example, 3-10.

A highly stressed dielectric material, such as a tensile stressed material, may be deposited in a conformal manner so as to respect any deposition constraints caused by pronounced surface topography of highly scaled semiconductor devices, followed by the deposition of a buffer material having enhanced gap-filling capabilities. Thereafter, a further stress-inducing layer is deposited to form a doublet structure, which acts on the transistor elements, thereby enhancing overall performance, without increasing the probability of creating deposition-related irregularities. Hence, production yield as well as performance of highly scaled semiconductor devices may be increased.

The invention discloses an enhanced grooved Schottky diode rectification device. Grooves extend from the upper surface of an epitaxial layer to a middle part of the epitaxial layer, a monocrystalline silicon boss of a first conductive type is formed at the region of the epitaxial layer between the adjacent grooves, Schottky barrier contact is formed between the top surface of the monocrystalline silicon boss and an upper metal layer, a gate groove is arranged in the grooves and filled with conductive polycrystalline silicon, ohmic contact is formed between the conductive polycrystalline silicon and the upper metal layer, the gate groove and the epitaxial layer are isolated by silicon dioxide, a doped region of a second conductive type is arranged in the monocrystalline silicon boss and attached to the side surface of the groove, the heavily-doped region of the second conductive type is arranged between the top of the doped region of the second conductive type and the upper surface of the epitaxial layer, both the doped region of the second conductive type and the heavily-doped region of the second conductive type form a pn junction interface with the epitaxial layer. The device of the invention modulates electric field distribution of a device during reverse bias, enhances a reverse voltage blocking capacity of the device, and provides more flexibility for performance adjustment of the device.

A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed to conformally cover the recess. A first titanium nitride layer is formed to conformally cover the titanium layer, thereby the first titanium nitride layer having first sidewall parts. The first sidewall parts of the first titanium nitride layer are pulled back, thereby second sidewall parts being formed. A second titanium nitride layer is formed to cover the recess. Moreover, a semiconductor structure formed by said semiconductor process is also provided.

A highly stressed dielectric material, such as a tensile stressed material, may be deposited in a conformal manner so as to respect any deposition constraints caused by pronounced surface topography of highly scaled semiconductor devices, followed by the deposition of a buffer material having enhanced gap-filling capabilities. Thereafter, a further stress-inducing layer is deposited to form a doublet structure, which acts on the transistor elements, thereby enhancing overall performance, without increasing the probability of creating deposition-related irregularities. Hence, production yield as well as performance of highly scaled semiconductor devices may be increased.

The present disclosure provides fin field-effect transistors and fabrication methods thereof. An exemplary fabrication process includes providing a substrate having a first region and a second region; forming first fins in the first region and second fins in the second region; forming a liner oxide layer on side surfaces of the first fins, the second fins and a surface of the substrate; forming an insulating barrier layer on the liner oxide layer in the first region; forming a precursor material layer on the insulating barrier layer in the first region and on the liner oxide layer in the second region; performing a curing annealing process to convert the precursor material into an insulation layer; and removing a top portion of the insulation layer to form an isolating layer and removing portions of the liner oxide layer, the insulating barrier layer, the first oxide layer and the second oxide layer.

An integrated circuit structure and a method of forming the same are provided. The method includes providing a surface; performing an ionized oxygen treatment to the surface; forming an initial layer comprising silicon oxide using first process gases comprising a first oxygen-containing gas and tetraethoxysilane (TEOS); and forming a silicate glass over the initial layer. The method may further include forming a buffer layer using second process gases comprising a second oxygen-containing gas and TEOS, wherein the first and the second process gases have different oxygen-to-TEOS ratio.

The present disclosure provides a method of fabricating a semiconductor structure, and the method includes following steps. A gate structure is formed on a substrate, and a liner layer is formed to cover the gate structure and the substrate. A spacer layer is formed on the liner layer, and an etching gas is continuously provided to remove a portion of the spacer layer while maintaining the substrate at a second pressure, which the etching gas has a first pressure. The second pressure is greater than the first pressure.

The invention provides a semiconductor device and a manufacturing method therefore, and an electronic apparatus. The manufacturing method comprises the steps of providing a semiconductor substrate, wherein a grid electrode structure is formed in the semiconductor substrate; forming an oxygen-rich laying layer on the top and side wall of the grid electrode structure and the semiconductor substrate; performing operations of disposition and curing treatment on a flowable dielectric material circularly on the oxygen-rich laying layer to form an inter-layer dielectric layer; and performing annealing treatment. According to the manufacturing method for the semiconductor device, due to the adoption of the oxygen-rich laying layer, the conversion of the flowable dielectric material can be promoted, and voids in the inter-layer dielectric layer are avoided; a high-temperature thermal annealing treatment step is not required to improve the gap filling of the dielectric layer; and therefore, the manufacturing method can improve the gap filling capability of the dielectric layer, and can improve the quality of the dielectric layer without increasing thermal budget.