The invention provides a
chip stack packaging structure and a manufacturing method thereof, the packaging structure comprises: a substrate, a first
chip, a circuit substrate and a second
chip, wherein, the substrate is provided with a first surface and an opposite second surface, the first chip is positioned at the first surface of the substrate, provided with a first driving surface and an opposite first
wafer backside, and electrically connected with the substrate by the
flip chip packaging bonding mode. The circuit substrate is formed on the first
wafer backside, comprising a
dielectric layer which is arranged on the first
wafer backside and a patterned circuit layer which is formed on the
dielectric layer, and the patterned circuit layer is electrically connected with the substrate by a wire bond. The second chip is positioned on the patterned circuit layer, comprising a second driving surface and at least one second
welding pad which is arranged on the second driving surface, wherein, the
welding pad is electrically connected with the patterned circuit layer and further electrically connected with the substrate by the wire bond.