31results about How to "Reduce signal transmission delay" patented technology

The invention belongs to the field of electronic ceramic materials, and provides a low thermal expansion cordierite-based glass-ceramic material and a preparation method thereof, which are used for ultra-large-scale integrated circuit packaging. The glass-ceramic material of the present invention is composed according to the mass percentage: MgO is 15-19wt%, Al 2 o 3 26~30wt%, SiO 2 46~50wt%, ZrO 2 2~6wt%, B 2 o 3 1~5wt%, K 2 O is 1 ~ 3wt%; by introducing K 2 O as modifier, ZrO 2 As a crystal nucleating agent, B 2 o 3 As a fever reducer, it inhibits a part (MgAl 2 Si 3 o 10 ) 0.6 phase inversion to Mg 2 al 4 Si 5 o 18 phase, thereby adjusting the coefficient of thermal expansion towards the Si chip (3.5×10 ‑6 / ℃), and at 2.5~3.5×10 ‑6 / °C adjustable, good thermal stability; at the same time, the bending strength can reach 150-200MPa, the Young's modulus can reach 80-95GPa, the dielectric constant is 5-6 (@1MHz), and the dielectric loss is 0.5-1× 10 ‑3 (@1MHz), which can increase the signal transmission speed and greatly reduce power consumption; in summary, the low thermal expansion cordierite-based glass-ceramic material of the present invention is suitable for VLSI packaging, which can significantly reduce signal transmission delay and power consumption , well matched with silicon chips.

The connector has terminals (20) i.e. signal terminals, arranged in an insulated housing (10), where the housing has a fixed part and an air-opening part. An earth contact (30) is provided for producing earth shielding and separated from the housing, where the earth contact passes through the terminals. An opening (31) is provided in the earth contact and formed corresponding to the fixed part of the housing. The fixed part has a reinforcing rib, and a projecting partial area (11) is formed at perforation areas of the housing, where the housing has a flat plate assembly.

The invention discloses a multi-chip package, comprising: a substrate, which is provided with a substrate circuit and has a first surface and a second surface opposite to the first surface, wherein a central groove is formed on the first surface, and a second surface is formed on the second surface. The surface is symmetrically formed with at least one pair of second surface grooves with respect to the center of the central groove; the chip set, each chip is arranged in the central groove and each second surface groove in equal numbers, and is matched with the substrate circuit an electrical connection; and an encapsulation layer, encapsulating the chipset on the substrate, thereby protecting each chip. According to the present invention, the problems of signal transmission delay and signal asynchrony during multi-chip packaging can be effectively reduced.