33results about How to "Low voltage operation" patented technology

A temperature sensor comprises (a) a first voltage generating circuit that generates and outputs a first voltage having a positive or negative temperature coefficient in proportion to the absolute temperature; (b) a second voltage generating circuit that generates a second voltage having an opposite sign of temperature coefficient compared to the first voltage and outputs a reference voltage that does not have a temperature coefficient based on the second voltage; and (c) a comparator that compares the first voltage output from the first voltage generating circuit with the reference voltage output from the second voltage generating circuit.

Semiconductor fabrication methods and structures, devices and integrated circuits characterized by enhanced operating performance. The structures generally include first and second source / drain regions formed in a body of a semiconductor material and a channel region defined in the body between the first and second source / drain regions. Disposed in at least one of the first and second source / drain regions are a plurality of plugs each formed from a volume-expanded material that transfers compressive stress to the channel region. The compressively strained channel region may be useful, for example, for improving the operating performance of p-channel field effect transistors (PFET's).

A temperature sensor comprises (a) a first voltage generating circuit that generates and outputs a first voltage having a positive or negative temperature coefficient in proportion to the absolute temperature; (b) a second voltage generating circuit that generates a second voltage having an opposite sign of temperature coefficient compared to the first voltage and outputs a reference voltage that does not have a temperature coefficient based on the second voltage; and (c) a comparator that compares the first voltage output from the first voltage generating circuit with the reference voltage output from the second voltage generating circuit.

Microelectronic structures and devices, and method of fabricating a three-dimensional microelectronic structure is provided, comprising passing a first precursor material for a selected three-dimensional microelectronic structure into a reaction chamber at temperatures sufficient to maintain said precursor material in a predominantly gaseous state; maintaining said reaction chamber under sufficient pressures to enhance formation of a first portion of said three-dimensional microelectronic structure; applying an electric field between an electrode and said microelectronic structure at a desired point under conditions whereat said first portion of a selected three-dimensional microelectronic structure is formed from said first precursor material; positionally adjusting either said formed three-dimensional microelectronic structure or said electrode whereby further controlled growth of said three-dimensional microelectronic structure occurs; passing a second precursor material for a selected three-dimensional microelectronic structure into a reaction chamber at temperatures sufficient to maintain said precursor material in a predominantly gaseous state; maintaining said reaction chamber under sufficient pressures whereby a second portion of said three-dimensional microelectronic structure formation is enhanced; applying an electric field between an electrode and said microelectronic structure at a desired point under conditions whereat said second portion of a selected three-dimensional microelectronic structure is formed from said second precursor material; and, positionally adjusting either said formed three-dimensional microelectronic structure or said electrode whereby further controlled growth of said three-dimensional microelectronic structure occurs.

An electrically erasable programmable read-only memory includes a first polysilicon layer, a second polysilicon layer and a third polysilicon layer, the first polysilicon layer and the third polysilicon layer forming a control gate and the second polysilicon layer forming a floating gate. The first polysilicon layer is horizontally disposed in series with the second polysilicon layer and is connected to the third polysilicon layer, so that the control gate encloses all of the floating gate except for a tunnel surface of the floating gate.

An electrically erasable programmable read-only memory includes a first polysilicon layer, a second polysilicon layer and a third polysilicon layer, the first polysilicon layer and the third polysilicon layer forming a control gate and the second polysilicon layer forming a floating gate. The first polysilicon layer is horizontally disposed in series with the second polysilicon layer and is connected to the third polysilicon layer, so that the control gate encloses all of the floating gate except for a tunnel surface of the floating gate.

A light emitting element driving circuit for driving a light emitting element in accordance with a differential data signal for causing the light emitting element to turn on or turn off is provided. The circuit includes a first transistor, a first constant current source connected to a drain and gate of the first transistor and configured to supply a constant current through the drain and source of the first transistor, a second transistor configured to supply a certain current, and a control circuit configured to electrically connect or disconnect the gate of the first transistor to or from a gate of the second transistor via a first resistor. The control circuit may supply, to the gate of the second transistor, an intermediate potential in accordance with the other of the differential data signals, while the gate of the first transistor is electrically disconnected from the gate of the second transistor.

The present invention provides with an electron-accepting compound having a structure of the following formula (1):