80results about How to "Lower gate voltage" patented technology

A circuit and method for reducing losses in a DC / DC converter by optimizing gate drive voltage. The circuit and method detect a change in the output load, or more specifically the output current, and adjust the gate voltage accordingly; in other words, providing adaptive gate drive voltage. In response to a reduction of output current, the invention reduces the gate voltage so as to reduce both conduction and switching losses in the semiconductor switching devices in the output stage.

A nanowire wrap-gate transistor is realised in a semiconductor material with a band gap narrower than Si. The strain relaxation in the nanowires allows the transistor to be placed on a large variety of substrates and heterostructures to be incorporated in the device. Various types of heterostructures should be introduced in the transistor to reduce the output conductance via reduced impact ionization rate, increase the current on / off ratio, reduction of the sub-threshold slope, reduction of transistor contact resistance and improved thermal stability. The parasitic capacitances should be minimized by the use of semi-insulating substrates and the use of cross-bar geometry between the source and drain access regions. The transistor may find applications in digital high frequency and low power circuits as well as in analogue high frequency circuits.

A TFT having a high threshold voltage is connected to the source electrode of each TFT that constitutes a CMOS circuit. In another aspect, pixel thin-film transistors are constructed such that a thin-film transistor more distant from a gate line drive circuit has a lower threshold voltage. In a further aspect, a control film that is removable in a later step is formed on the surface of the channel forming region of a TFT, and doping is performed from above the control film.

The amplifier circuit (1) includes a differential pair of PMOS transistors at input (P3, P4), whose source receives a current from a current source (3). The gate of the first transistor (P3) of the pair defines a non-inverting input (XOUT) and the gate of the second transistor (P4) of the pair defines an inverting input (XIN). A drain of the first transistor (P3) of the differential pair is connected to a diode connected NMOS transistor (N2) of a first current mirror (N1, N2), and a drain of the second transistor (P4) of the differential pair is connected to a diode connected NMOS transistor (N3) of a second current mirror (N3, N4). A diode connected PMOS transistor (P2) of a third current mirror is connected to the drain of a second NMOS transistor (N4) of the second current mirror, while a drain of a second PMOS transistor (P1) of the third current mirror is connected to the drain of a second NMOS transistor (N1) of the first current mirror to define a first output (OUT1), which is inverted by a reverser (N5, P7) to supply an inverted output signal (OUT) capable of varying rail to rail. A first complementary NMOS transistor (N6) is connected in the form of a reverser with the first PMOS transistor (P3) of the differential pair. A second complementary NMOS transistor (N7) is connected in the form of a reverser with the second MOS transistor (P4) of the differential pair.

The present invention relates to a symmetric quadrupole structured field emission display without spacer comprising the upper and under substrates with a dielectric layer in between, wherein comb-like dielectric layer with lateral connection belts and a number of longitudinal working belts and longitudinal anodes are arranged on the upper substrate, bus electrodes are arranged longitudinally along the center on each anode, on the top, longitudinal alternating phosphor layer and dielectric layer for isolation on anode, gate electrodes are arranged on both sides of each longitudinal work belts, with the bus electrode as symmetry center, forming interdigital gate electrodes, horizontal cathode electrodes and longitudinal auxiliary electrodes are on the under substrate, resistor layer for current limiting and dielectric layer for cathode protection are arranged alternating horizontally on each cathode electrode, each intersect of the auxiliary electrode and cathode is isolated by the dielectric layer for cathode.