Patents
Literature
Hiro is an intelligent assistant for R&D personnel, combined with Patent DNA, to facilitate innovative research.
Hiro

129results about How to "Large memory capacity" patented technology

Memory extending system and memory extending method

ActiveCN103488436ALarge memory capacityAvoid the problem of redundant processing powerInput/output to record carriersComputer architectureQuick path interconnect
An embodiment of the invention discloses a memory extending system and a memory extending method. The system comprises processors, extended memories, extended chips and multiple processor installation positions, and a memory installation position is arranged at each process installation position; the processor installation positions are connected mutually through QPI (quick path interconnect) interfaces, at least one processor installation position is provided with a processor, and at least one of the rest installation positions serves as extended installation position; the extended chips are installed in the extended installation position; the extended memories are installed to the memory installation positions connected with the extended chips. The memory extending system has the advantages that the extended chips are mounted at other processor installation positions to replace the processors, and the existing processors are enabled to be capable of accessing the extended memories carried by the extended chips through the extended chips, so that memory capacity of the existing processors is increased on the condition that processing capacity is not improved, and the problem of processing capacity redundancy caused by the fact that memories are extended by adding processors in the prior art is solved.
Owner:XFUSION DIGITAL TECH CO LTD

Failure analysis system of semiconductor memory device

In failure analysis method of a semiconductor memory device, an absolute value of a position difference between two fail bits of a two-dimensional bit map is calculated while a histogram corresponding to the absolute value of the position difference is updated. The bit map indicates a map of fail bits and each fail bit corresponds to a fail memory cell. The above calculation is repeated to all combinations of two of the fail bits in the bit map. Then, an expectation function value is calculated for each of values from the histograms and the number of the fail bits. Finally, whether the fail bits has regularity or irregularity for each value is determined based on the calculated expectation function value for the value.
Owner:RENESAS ELECTRONICS CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products