225results about How to "Improve testability" patented technology

A semiconductor device with a sheet-like insulating substrate (101) integral with two or more patterned layers of conductive lines and vias, a chip attached to an assembly site, and contact pads (103) in pad locations has an encapsulated region on the top surface of the substrate, extending to the edge of the substrate, enclosing the chip, and having contact apertures (703) at the pad locations for external communication with the pad metal surfaces. The apertures may have not-smooth sidewall surfaces and may be filled with solder material (704) to contact the pads. Metal-filled surface grooves (710) in the encapsulated region, with smooth groove bottom and sidewalls, are selected to serve as customized routing interconnections, or redistribution lines, between selected apertures and thus to facilitate the coupling with another semiconductor device to form a package-on-package assembly.

A build-up structure for chip to chip interconnects and System-In-Package utilizing multi-angle vias for electrical and optical routing or bussing of electronic information and controlled CTE dielectrics including mesocomposites to achieve optimum electrical and optical performance of monolithic structures. Die, multiple die, Microelectromechanical Machines (MEMs) and / or other active or passive components such as transducers or capacitors can be accurately positioned on a substrate such as a copper heatsink and multi-angle stud bumps can be placed on the active sites of the components. A first dielectric layer is preferably placed on the components, thereby embedding the components in the structure. Through various processes of photolithography, laser machining, soft lithography or anisotropic conductive film bonding, escape routing and circuitry is formed on the first metal layer. Additional dielectric layers and metal circuitry are formed utilizing multi-angle vias to form escape routing from tight pitch bond pads on the die to other active and passive components. Multi-angle vias can carry electrical or optical information in the form of digital or analog electromagnetic current, or in the form of visible or non-visible optical bussing and interconnections.

A circuit and method for testing a transceiver. The circuit includes a bit pattern generator connected to the transceiver such that the bit pattern generator can communicate a serial data stream to a receiver portion of the transceiver. The circuit also includes a bit pattern checker connected to the transceiver such that a transmitter portion of the transceiver can communicate a serial data stream to the bit pattern checker. The transceiver is configured such that the receiver portion of the transceiver is communicatingly looped back to the transmitter portion of the transceiver such that a data stream can be communicated from the receiver portion of the transceiver to the transmitter portion of the transceiver. Desirably, a loopback circuit in connected to the transceiver and includes fixed bit pattern means for communicating at least one fixed bit pattern to the transmitter portion of the transceiver. The loopback circuit is configured such that the FIFO component receives a set of bits from the receiver portion of the transceiver and at least one of the bits in the set is replaced by the fixed bit pattern before being communicated to the transmitter portion of the receiver.

The invention relates to an intelligent distributing manager which comprises power module with low voltage, communication module, alternative-direct current detecting module, electric remote terminal and load detecting module. Wherein, the CPU of electric remote terminal is central processor, to collect and process parallel data, and analyze and send the load state to the system controller; the memory stores operation program, parameter and operation state. The manger via communication module and system bus is connected to the system control center, to receive instruction feedback; the load detecting module comprises several alternative-direct current solid power controllers, via internal bus to connect the electric remote terminal; the alternative-direct detecting module real time detects the voltage of each collecting bar of power. The invention is distributed secondary distributing manager, via system bus to connect the control center. The invention can power load, reduce cable length, reduce cost and improve reliability, with self-detection and protection.

A build-up structure for chip to chip interconnects and System-In-Package utilizing multi-angle vias for electrical and optical routing or bussing of electronic information and controlled CTE dielectrics including mesocomposites to achieve optimum electrical and optical performance of monolithic structures. Die, multiple die, Microelectromechanical Machines (MEMs) and / or other active or passive components such as transducers or capacitors can be accurately positioned on a substrate such as a copper heatsink and multi-angle stud bumps can be placed on the active sites of the components. A first dielectric layer is preferably placed on the components, thereby embedding the components in the structure. Through various processes of photolithography, laser machining, soft lithography or anisotropic conductive film bonding, escape routing and circuitry is formed on the first metal layer. Additional dielectric layers and metal circuitry are formed utilizing multi-angle vias to form escape routing from tight pitch bond pads on the die to other active and passive components. Multi-angle vias can carry electrical or optical information in the form of digital or analog electromagnetic current, or in the form of visible or non-visible optical bussing and interconnections.

A semiconductor device with a sheet-like insulating substrate (101) integral with two or more patterned layers of conductive lines and vias, a chip attached to an assembly site, and contact pads (103) in pad locations has an encapsulated region on the top surface of the substrate, extending to the edge of the substrate, enclosing the chip, and having contact apertures (703) at the pad locations for external communication with the pad metal surfaces. The apertures may have not-smooth sidewall surfaces and may be filled with solder material (704) to contact the pads. Metal-filled surface grooves (710) in the encapsulated region, with smooth groove bottom and sidewalls, are selected to serve as customized routing interconnections, or redistribution lines, between selected apertures and thus to facilitate the coupling with another semiconductor device to form a package-on-package assembly.

To provide a piezoelectric oscillator in which, even after a first package and a second package are bonded to each other, the connection state can be easily observed externally, so that testability can be enhanced, and connection failure can be easily found out to perform a repair. A piezoelectric oscillator includes a first package housing a piezoelectric resonator element therein and having external terminal portions connected to excitation electrodes of the piezoelectric resonator element, and a second package housing an oscillating circuit element, the first package being superposed on and fixed to the second package. Herein, in the second package, the oscillating circuit element, which is connected to a lead frame, is molded out of resin, and connection terminal portions and mounting terminals formed of the lead frame are exposed at the second package. Furthermore, the external terminal portions of the first package are exposed at the side surfaces of the first package, and the external terminal portions and the connection terminal portions of the second package are electrically connected to each other by a conductive material.

Computer system and method enforces control policies including access and usage policies. A rules-based engine member or assembly is coupled between a rights-management (or similar) system and one or more target applications. The rules-based engine member centralizes data security determinations for the target applications. One or more agents are responsive to the rules-based engine member and target applications, and handle low-level details in interactions between the rules-based engine member and target applications. A generic engine framework serves as a normalizing factor and enables scalability.

A testing device for a semiconductor storage device suppresses the increase in the circuit size, provides for facilitated accommodation to a test with frequent changes in the test pattern, and improves testability of the semiconductor storage device. A plurality of holding circuits are provided holding write data for memory cells of a memory cell array. (Original) The write data from the holding circuits are written in the memory cells of the selected address. A plurality of comparators are supplied with data read out from the memory cells and with data held by the holding circuits as expectation data to compare the readout data and the expectation data. The non-inverted or inverted value of the write data held by the holding circuits is output as the write data to the memory cells and as expectation data to the comparators depending on the value of the inversion control signal.

The invention provides a device for spreading spectrum of a reference clock signal and a method thereof, wherein, the device comprises a divider which is used for receiving an M value and an N value, generating a first floating point decimal according to the M value and the N value, and sending the first floating point decimal to a spread spectrum control generator; the spread spectrum control generator which is used for receiving the first floating point decimal from the divider and the reference clock signal from an analog circuit, generating a second floating point decimal for spreading the spectrum according to the first floating point decimal, the reference clock signal and modulation frequency, and sending the second floating point decimal to a delta sigma modulator; the delta sigma modulator which is used for generating a first integer distribution according to the second floating point decimal and sending the first integer distribution to the analog circuit; and the analog circuit which is used for sending the external reference clock signal to the spread spectrum control generator, generating a first frequency division clock signal according to the first integer distribution, and comparing and adjusting phases of the first frequency division clock signal, and spreading the spectrum of the reference clock signal.

The invention belongs to the technical field of integrated circuit, and essentially relates to a one-time programming memory and a storing method. A metal oxide with two or more elements and the capability of repeated programming is used in the memory as storing media. Different voltages with different polarities are applied on both ends of the storing media for programming and erasing operations. The storing media of the invention has the capability of repeated programming, so the memory of the invention can be intelligently erased and tested for repeated programming. The yield rate and reliability of the memory of the invention are both increased, and the memory has low power consumption, high yield rate and high capacity matrix blocks.

The invention provides a data interaction system with a plurality of external interfaces, which comprises a plurality of external main control end modules, a plurality of external interface modules and interface conversion modules, wherein the external main control end modules correspond to the external interface module, command words and data are predefined according to an interaction protocol with an internal bus and are transmitted through the external interface modules, the external interface modules are respectively used for transmitting the corresponding command words and the data to the interface conversion modules, and the interface conversion modules analyze and convert the command words and the data according to the data interaction protocol for executing the data interaction with the internal bus. The invention can improve the consistency and the importance of the interactive design of the external interfaces and the internal data.

The invention discloses a test system for intelligently diagnosing faults of a high-integration digital signal processing system, and aims to solve the problem of low fault diagnosis capability of anexisting boundary scanning test system. According to the technical scheme, an intelligent test platform management unit operates control software, collects data of multichannel signals, generates a test sequence, allocates physical addresses to all modules, lists all the modules connected to a system backboard on a software interface, processes the multichannel data and diagnoses faults; the control software calls boundary scanning test software to generate a test vector for the tested module, applies the test vector to the chip core logic input end to form a circuit fault criterion, and sendsthe circuit fault criterion to the boundary scanning controller; the test vectors of different regions are loaded to a tested module to generate a fault injection vector, and the fault injection vector is transmitted to a fault injection controller; and the fault injection vector is loaded to the tested module to complete the fault diagnosis of the multichannel signal processing subrack platformmodule-level digital chip.

The invention provides a test method for command line interface and a device thereof; the method includes the following procedures: firstly, an aggregation command which needs to be tested is acquired; secondly, from the beginning of the root node of the aggregation command, the aggregation command is made the equivalence binary tree conversion; thirdly, the leaf node of the equivalence binary tree undergoes traverse, the route between the leaf node and the root node is accessed, each single command and the expectation prompting message corresponding to the single command are acquired; fourthly, each single command is tested. By the equivalence binary tree conversion, the structure of the command tree is simplified; moreover, the constructed command tree is easy to test, thereby enhancing the testability, reducing the waste of computing resource of equipment and greatly improving the test efficiency.

An improved semiconductor device package is manufactured by attaching semiconductor chips (130) on an insulating substrate (101) having contact pads (103). A mold is provided, which has a top portion (210) with metal protrusions (202) at locations matching the pad locations. The protrusions are shaped as truncated cones. The substrate and the chips are loaded onto the bottom mold portion (310); the mold is closed by clamping the top portion onto the bottom portion so that the protrusions approach the contact pads. Encapsulation compound is introduced into the cavity and the protrusions create apertures through the encapsulation compound towards the pad locations.