System and method for debugging multiple field-programmable gate arrays
A gate array and on-site technology, applied in the field of multi-chip FPGA debugging system, can solve the problems of multi-storage resources, time-consuming, multi-pins, etc., and achieve the effects of improving efficiency, saving pins, and saving compilation times
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[0040] The technical solutions of the present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments. It should be understood that the following examples are only used to illustrate and explain the present invention, but not to limit the technical solution of the present invention.
[0041] Such as figure 1 Shown, represented the structure of the system embodiment of multi-chip FPGA debugging of the present invention, including a special-purpose test FPGA, multi-chip FPGA to be tested and debugging host, wherein:
[0042]The FPGA to be tested is connected to a dedicated test FPGA through a high-speed serial bus, and connected to a debugging host through a serial bus, which is used to instantiate the signal selection and transmission modules of this chip to select and group the signals to be tested according to the clock domain; In the test working mode, according to the selection of the debugging host, the signal grou...
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