1003 results about "Anisotropic conductive film" patented technology

A build-up structure for chip to chip interconnects and System-In-Package utilizing multi-angle vias for electrical and optical routing or bussing of electronic information and controlled CTE dielectrics including mesocomposites to achieve optimum electrical and optical performance of monolithic structures. Die, multiple die, Microelectromechanical Machines (MEMs) and / or other active or passive components such as transducers or capacitors can be accurately positioned on a substrate such as a copper heatsink and multi-angle stud bumps can be placed on the active sites of the components. A first dielectric layer is preferably placed on the components, thereby embedding the components in the structure. Through various processes of photolithography, laser machining, soft lithography or anisotropic conductive film bonding, escape routing and circuitry is formed on the first metal layer. Additional dielectric layers and metal circuitry are formed utilizing multi-angle vias to form escape routing from tight pitch bond pads on the die to other active and passive components. Multi-angle vias can carry electrical or optical information in the form of digital or analog electromagnetic current, or in the form of visible or non-visible optical bussing and interconnections.

An object is to efficiently manufacture an organic EL display. A circuit substrate 10 in which is set microstructures 12 and which is formed with wiring 14, and a transparent substrate 20 formed with a transparent electrode 21, an emissive layer 25 and a cathode layer 26, are stuck together with the side formed with the wiring 14 and the side formed with the cathode layer 26 facing the inside, to thereby manufacture an organic EL display 30. In the sticking together of the circuit substrate 10 and the transparent substrate 20, an anisotropic conductive paste or an anisotropic conductive film can be used.

A flexible printed circuit with a broadened anisotropic conductive film is provided. The flexible printed circuit includes a substrate layer and a circuit layer, characterized in that a pitch of the anisotropic conductive film is broadened to be ranged from 0.5 mm to 3.0 mm. It has even and low impedance, even breakage of conductive particles, even pressure, and thus has good reliability of the anisotropic conductive film for use in handheld electronic devices.

A build-up structure for chip to chip interconnects and System-In-Package utilizing multi-angle vias for electrical and optical routing or bussing of electronic information and controlled CTE dielectrics including mesocomposites to achieve optimum electrical and optical performance of monolithic structures. Die, multiple die, Microelectromechanical Machines (MEMs) and / or other active or passive components such as transducers or capacitors can be accurately positioned on a substrate such as a copper heatsink and multi-angle stud bumps can be placed on the active sites of the components. A first dielectric layer is preferably placed on the components, thereby embedding the components in the structure. Through various processes of photolithography, laser machining, soft lithography or anisotropic conductive film bonding, escape routing and circuitry is formed on the first metal layer. Additional dielectric layers and metal circuitry are formed utilizing multi-angle vias to form escape routing from tight pitch bond pads on the die to other active and passive components. Multi-angle vias can carry electrical or optical information in the form of digital or analog electromagnetic current, or in the form of visible or non-visible optical bussing and interconnections.

The present invention provides systems and methods for assembling an electronic assembly using an anisotropic conducting membrane (ACM) as a component interconnect and a substrate embossed with placement cavities or a positional fixture to facilitate component placement on the substrate in the electronic assembly. The fixture may comprise multiple layers of interconnects to improve routing density for the electronic assembly enclosed in a housing. An alignment chain may be used to monitor positional and contact integrity of the ACM interfaced components in a complex assembly. The systems and methods allow components to be detached for reuse. Interconnection elements or conduction pathways at the components can be used to interconnect a plurality of neighboring substrates over the ACM layers into a stacked electronic assembly.

In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are separated by a mechanical spacer (such as a filler material or an adhesive). Moreover, the chip package includes a substrate at a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the substrate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as: solder, stud bumps, plated traces, wire bonds, spring connectors, a conductive adhesive and / or an anisotropic conducting film. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the substrate.

The invention is intended for providing a semiconductor package structure which prevents degradation in characteristics of a semiconductor device, and breakage of interconnections, when the semiconductor device is packaged on a circuit substrate. In the package structure having the semiconductor device mounted on the circuit substrate, bump electrodes of the semiconductor device are placed on input / output terminal electrodes of the circuit substrate and are electrically and mechanically connected thereto by bonding with a conductive adhesive, and the semiconductor device is bonded and fixed to the circuit substrate by a resin film formed previously on a surface of a main body of the circuit substrate. The structure does no damage to a semiconductor functional part and to interconnections, and allows mounting with a lower load as compared to structures using conventional anisotropic conductive films and the like.

A method for producing an emissive pixel screen includes forming an active pixel matrix along which an electrode forming layer runs and having pixels arranged according to a distribution, forming an anisotropic substrate that includes a set of light emitting diodes constituted by parallel nanowires and arranged in an insulating matrix transversely with respect to a substrate thickness and having a density higher than a density of the pixels irrespective of the pixel distribution, connecting the substrate to the active pixel matrix by connecting only sub-groups of the parallel nanowires by a first end to separate pixel electrodes defined in the electrode forming layer according to the distribution of the pixels in the matrix, and connecting the sub-groups, by another end, to a common electrode, and delimiting the sub-groups by rendering the nanowires of the substrate that are arranged between the sub-groups emissively inactive.

A semiconductor chip and manufacturing method thereof, the semiconductor chip including a plurality of bumps connected to a driving circuit integrated on a semiconductor substrate and an organic insulating layer disposed on the driving circuit. The organic insulating layer extends from the semiconductor substrate less than the plurality of bumps such that a lower edge of the plurality of bumps protrudes further than a lower edge of the organic insulating layer.

This invention provides an electroconductive particle placement sheet comprising electroconductive particles and an insulating resin sheet. The thickness of the insulating resin sheet is smaller than the average particle diameter of the electroconductive particles. Electroconductive particles are protruded from the reference plane (P1) on at least one side of the insulating resin sheet. The electroconductive particle in is part protruded from the reference plane (P1) is covered with a layer formed of the same resin as in the insulating resin sheet. The electroconductive particle placement sheet is characterized by satisfying a relationship of h1 > h2 wherein h1 represents an average protrusion height, which is the average of distance between the reference plane (P1) and a tangential line (L1), which is a tangential line parallel to the reference plane (P1) of the electroconductive particle and is in contact with the part protruded from the reference plane (P1), and h2 represents an average protrusion height which is the average of distance between the reference plane (P2) and a tangential line (L2), which is a tangential line parallel to the reference plane (P2) of the electroconductive particle and is on the side opposite to the tangential line (L1), provided that, when the tangential line (L2) is within the insulating resin sheet, h2 < 0; when the tangential line (L2) is on the reference plane (P2), h2 = 0; and when the tangential line (L2) is outside the insulating resin sheet, h2 > 0.