65 results about "Circuit sizing" patented technology

An antenna circuit includes a plurality of antenna circuit units on a circuit substrate. The plurality of antenna circuit units includes: a large antenna circuit unit whose circuit size is large; and a small antenna circuit unit whose circuit size is smaller than the size of the large antenna circuit unit, the small antenna circuit unit provided inside the large antenna circuit unit and provided detachable from the large antenna circuit unit.

A sensing circuit for multi-level flash memory is disclosed. The advantages of the sensing circuit are reducing the circuit size, reducing the testing time for tuning reference voltage and maintaining a constant difference between two approximate reference voltages. The sensing circuit comprises a reference voltage generator which includes a number of serial connected resistive devices and provides several reference voltages by voltage division; a data saving circuit outputs a data voltage; a comparing circuit compares the data voltage with the several reference voltages to output a comparing signal; a decoder receives and then decodes the comparing signal to output the data.

A method of programming a nonvolatile memory device using hybrid local boosting which includes a plurality of cell strings each having a plurality of electrically erasable and programmable memory cells connected in series and a plurality of wordlines respectively connected to control gates of the plurality of memory cells. The address of a selected cell that is to be programmed is received. A determination is made as to whether a selected wordline connected to the selected cell is located above or under a reference wordline based on the received address. The selected cell is programmed using local boosting when the selected wordline corresponds to the reference wordline or is located above the reference wordline. The selected cell is programmed using self-boosting when the selected wordline is located under the reference wordline. The programming method reduces circuit size of a nonvolatile memory device employing the programming method and efficiently prevents program disturbance due to charge sharing.

The invention provides a multi-layer power distribution network of high-frequency printed boards based on accessory resistive films. The multi-layer power distribution network of the copper-clad plates based on the accessory resistive films is formed by overlaying multiple layers of copper-clad plates, each layer of the multi-layer power distribution network is arranged to be of a strip line structure, lower-layer media of the strip line structures are core plates, and upper-layer media of the strip line structures are prepregs; stepped open grooves are formed in the multi-layer power distribution network to lead out signal lines so that the multi-layer power distribution network can be connected with other circuits conveniently; by utilizing a printed board multi-layer mixed pressing technology, the power distribution network and the other circuits are integrated through mixed pressing. By the adoption of the scheme, a lining plate and a shielding cavity are not needed, and the circuits are small in size and low in weight; isolating resistors are directly buried in the multiple layers of printed boards, punching is not needed, the isolating resistors are connected with a surface-layer resistor, different layers of the power distribution network are not affected mutually, and a power distribution network with more layers can be manufactured.

Provided is a semiconductor memory device using a single-bit line method that determines read operation timing in accordance with operation of a replica bit line. Further provided is a control method for the semiconductor memory device. Even when a transistor property fluctuation has occurred, the semiconductor memory device and the control method are capable of preventing, for example, increases in access time and circuit size and concurrently capable of reducing the occurrence probability of data readout error. The gate lengths of replica memory cell transistors are set as being values greater than the gate length of memory cell transistors. Thereby, a distribution center of a current drive capability distribution of the replica memory cell transistors is set lower than a distribution center of a current drive capability distribution of the memory cell transistors. Consequently, an occurrence probability of a delay in a voltage-fall start time on a regular data line can be reduced to be lower in comparison to a transmission timing of a latch control signal.

The invention discloses a novel anti-SEU (Single Event Upset) reinforcement storage cell based on crossly-coupled miller capacitors. The novel anti-SEU reinforcement storage cell comprises a storage cell. The novel anti-SEU reinforcement storage cell is characterized in that the storage cell is a DICE (Dual Interlocked storage Cell); a miller capacitor is arranged between each two nodes in four nodes of the DICE. The novel anti-SEU reinforcement storage cell has the beneficial effects that the crossly-coupled miller capacitors are connected among the nodes of the DICE so as to obtain relatively great capacitance by using small capacitance. On the aspect of a circuit size, the area of the device can not be obviously increased by the miller capacitors so as to meet the requirement that the size of an integrated size is smaller and smaller. The crossly-coupled miller capacitors are additionally arranged so that the critical load of overturning the nodes is increased, the change of voltage of each node, caused by collection loads with the same quantity, is reduced, the feedback delaying time between two phase inverters of the DICE is increased, the multi-point anti-SEU reinforcement capability of the DICE is improved, and a possible inversion phenomenon caused by that the two nodes are simultaneously influenced by radiation effects is avoided.

Provided in the invention is a cavity-based filtering balun which comprises a cavity resonator. An input terminal PCB board and an output terminal PCB board are arranged at the two opposite sides of the cavity resonator; an input terminal slot line is arranged at one side, approaching the side of the cavity resonator, of the input terminal PCB board; and an input terminal microstrip line is arranged at the other side. A first slot hole that corresponds to the input terminal slot line completely is arranged at the position corresponding to the input terminal slot line on the side wall of the input terminal PCB board at the cavity resonator; an output terminal slot line is arranged at one side, approaching the side of the cavity resonator, of the output terminal PCB board and an output microstrip line is arranged at the other end; and a second slot hole corresponding to the output terminal slot line completely is arranged at the position corresponding to the output terminal slot line, onthe side wall of the output terminal PCB board at the cavity resonator. According to the invention, the filtering balun body is a cavity resonator, so that the quality factor is improved and the insertion losses are reduced. With the two resonance modes in the cavity resonator, the bipolar transmission band requirement is realized in the single cavity structure; and the circuit dimension is reduced.

A semiconductor device with an improved arithmetic processing speed and a decreased circuit size, and its driving method are provided. In the semiconductor device, a first terminal of a first transistor and a gate of a second transistor are electrically connected to a first terminal of a capacitor, and a control circuit is electrically connected to a second terminal of the capacitor. The control circuit supplies a first potential to the second terminal of the capacitor, in other words, adds a value corresponding to the first potential to the value of first data previously retained in the gate of the second transistor in order to obtain second data. In the second transistor, the second data, specifically, a third potential commensurate with the potential of the gate will be output from a second terminal when a second potential is supplied to a first terminal.

The invention provides a shift register circuit, which is suitable for driving an organic LED display panel. The shift register circuit comprises a plurality of circuit levels in series connection. Each circuit level comprises two shift registers and an enable signal for generating circuit. The shift register comprises two transistors, an input unit and a forbidden energy unit. The enable signal generates circuit, so that an enable signal can be generated based on the signal of the control end of the four transistors in the two shift registers. The shift register circuit is advantageous in that the circuit design of each circuit level is relatively simple; circuit size is relatively small; cost is relatively low.

An improved voltage reduction circuit and method is described that incorporates an independently controllable back bias voltage for increased gate/bulk fields in isolation well voltage reduction transistors that couple to and reduce external voltages that are too high for the integrated circuit process technology limits. The improved voltage reduction circuit and method allows for a higher overall available voltage and current flow for regulation by the circuit. Additionally, the improved voltage reduction circuit and method reduces voltage reduction circuit size by allowing for efficient implementation in a single isolation well. Furthermore, the improved voltage reduction circuit and method includes a back bias voltage control circuit that turns on and regulates the back bias voltage and avoids the problem of reverse bias conditions.

Provided is a storage device wherein a voltage requiring control is reduced and a peripheral circuit scale is reduced. A first pulse voltage (VBLR) is supplied to an electrode (11) of a variable resistance element (10) from a first power supply (21) through a bit line (BLR), a second pulse voltage (VWL) for cell selection is supplied to a control terminal (20c) of a transistor (20) from a second power supply (22) through a word line (WL), and a third pulse voltage (VBLT) is supplied to a second input/output terminal (20b) of the transistor (20) from a third power supply (23) through the bit line (BLT). At the time of rewriting information, a cell voltage and a cell current can be varied (reduced or increased) by adjusting the voltage value (VBLT) of the third power supply (23) by the adjusting circuit (24).

The invention relates to a compact suspended microstrip high-isolation multi-power combiner. The compact suspended microstrip high-isolation multi-power combiner is composed of a suspended microstrippower dividing/combining circuit, a microstrip or suspended microstrip isolation circuit and connection coaxial cables; the suspended microstrip power dividing/combining circuit is composed of input ports, an output port, a dielectric substrate, metal microstrips, an upper grounding metal plate and a lower grounding metal plate; the isolation circuit adopts star connection, and an isolation resistor is installed on the isolation circuit; the suspended microstrip power dividing circuit achieves power allocation and input/output impedance matching; and the isolation circuit achieves good outputVSWR and isolation among the ports. The compact suspended microstrip high-isolation multi-power combiner has the advantages of being low in insertion loss, good in input/output echo, high in power capacity and isolation, wide in bandwidth, small in circuit size and the like, can be applied into various high-power microwave and millimeter wave systems and has the wide application prospect in systems of communication, radar, measurement and control and the like.

A highly efficient and reliable reproduced signal evaluation method and an optical disc drive using that method in which assuming that the number of 2T's appearing successively in a predetermined evaluation bitstream is i, the evaluation bitstream is divided into a main bitstream (5+2i) long and sub bitstreams at the ends of the main bitstream. The check process to determine whether a predetermined evaluation bitstream is included in the binarized bitstreams is replaced with a main bitstream agreement check. This can prevent an increase in the circuit size. At the same time, by separately summing up for each main bitstream the calculated results of Euclidean distance between the reproduced signal and the target signal corresponding to the evaluation bitstream, the size of an evaluation summing circuit can be reduced.