The present invention discloses a digital weight average
algorithm applied to a successive approximation register analog-to-
digital converter, characterized in that a pseudo-random
number generator is added in a circuit of the successive approximation register analog-to-
digital converter, a random pin code is generated by the pseudo-random
number generator before each quantization of the successive approximation register analog-to-
digital converter, and the connection of each unit
capacitor is determined by the pin code through successive approximation register
control logic, so that the unit capacitors form capacitors of different weights at random. In the present invention, the DWA
algorithm is applied to a structure of the SAR ADC, so that the
harmonic of an output
signal is suppressed to the
noise floor, to realize the first-order shaping of the
noise of the output
signal, thereby increasing the spurious-free
dynamic range of the SAR ADC; and when the number of times of quantification of the SAR ADC reaches a certain number, the DWA
algorithm enables
capacitor mismatch to be allocated to each quantization, to average the
capacitor mismatch, reduce the effect of the capacitor mismatch on the static characteristic and the dynamic characteristic of the SAR ADC, and improve the quantization accuracy of the SAR ADC.