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Low-density odd-even checking codec hardware simulation system based on programmable gate array

A low-density parity and hardware emulation technology, applied in the application of multi-bit parity error detection coding, error correction/detection using block codes, special data processing applications, etc., can solve the problem of rapid development of LDPC code research , time-consuming and other problems, to achieve the effect of shortening the simulation verification time, improving the noise quality, and speeding up the research process

Active Publication Date: 2008-02-27
南京宁麒智能计算芯片研究院有限公司
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Problems solved by technology

[0004] At the same time, in the study of LDPC codes, the verification of LDPC decoders is also an important task. Since the verification work takes a lot of time, it also brings troubles to the rapid development of LDPC code research.

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  • Low-density odd-even checking codec hardware simulation system based on programmable gate array
  • Low-density odd-even checking codec hardware simulation system based on programmable gate array
  • Low-density odd-even checking codec hardware simulation system based on programmable gate array

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Embodiment Construction

[0022] The present invention will be further described in detail below with reference to the accompanying drawings. In this embodiment, a (2209, 2021) Array LDPC code with code length N=2209 is selected, and the structure of the LDPC code is shown in FIG. 5 . where I is a 47×47 identity matrix, α i is the matrix formed after the identity matrix I is shifted by i bits.

[0023] The input clock of the simulation system is 100MHz, and two clocks of 120MHz and 40Hz are obtained through the processing of the digital phase-locked loop (DPLL) inside the FPGA. The entire FPGA hardware part except the decoder part works at 40MHz, and the other parts work at 120MHz.

[0024] 1 is a schematic structural diagram of an FPGA-based LDPC encoding / decoding hardware emulation system of the present invention, which includes a PC-side control software part and an FPGA-based hardware part. The FPGA hardware part includes PCI interface control module and LDPC code simulation module. The LDPC co...

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Abstract

The invention discloses a kind of LDPC encode and decode hardware emulate system basing on FPGA. The system includes the control software of PC terminal and the hardware basing on DPFA which includes the control module of PCI interface, random number generator, Gaussian noise generator, LDPC encoder / decoder and so on. The invention bases on FPGA hardware and realizes simulation study of the LDPC, at the same time, the system is good at controllability, observation and reusability, and improves the pace of simulation ( is more than 300 times higher than the pace of the simulation software), offering a good lab environment for researching the same kind of error correcting codes further.

Description

technical field [0001] The invention belongs to the technical field of digital communication, and relates to a hardware simulation system for a digital communication implementation scheme, which can be applied to the research of LDPC (Low-Density ParityCheck, low density parity check) codes and the verification of LDPC code decoders. Said to be a low density parity check codec hardware emulation system based on programmable gate array. Background technique [0002] Among the existing coding methods, the LDPC coding method has shown the coding performance close to the Shannon limit in some cases. LDPC codes have attracted worldwide attention due to their excellent performance, and are considered as one of the promising error correction coding methods in communication system applications. The research of LDPC codes has become a research hotspot in the field of digital communication. [0003] At present, the research field of LDPC codes mainly revolves around two aspects: one...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50H03M13/11
Inventor 李丽张仲金高明伦何书专李伟董岚张川
Owner 南京宁麒智能计算芯片研究院有限公司
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