151 results about "Identity matrix" patented technology

A method for decoding a multi-audio-object signal having audio signals of first and second types encoded therein, the multi-audio-object signal having a downmix signal and side information having level information of the audio signals of the first and second types in a first predetermined time/frequency resolution, the method including computing a prediction coefficient matrix C based on the level information; and up-mixing the downmix signal based on the prediction coefficients to obtain a first and/or a second up-mix audio signal approximating the audio signals of the first and second types, respectively, wherein up-mixing yields the first and/or second up-mix signals S₁ and S₂ from the downmix signal d according to a computation representable by

with “1” denoting—depending on the number of channels of d—a scalar, or an identity matrix, and D⁻¹ being a matrix uniquely determined by a downmix prescription according to which the audio signals of the first and second types are downmixed into the downmix signal, and which is also included by the side information, and H being a term independent from d.

A method for generating a parity check matrix of a block LDPC code is disclosed. The parity check matrix includes an information part corresponding to an information word and a first parity part and a second parity part each corresponding to a parity. The method includes determining a size of the parity check matrix based on a coding rate applied when coding the information word with the block LDPC code, and a codeword length; dividing a parity check matrix with the determined size into a predetermined number of blocks; classifying the blocks into blocks corresponding to the information part, blocks corresponding to the first parity part, and blocks corresponding to the second parity part; arranging permutation matrixes in predetermined blocks from among the blocks classified as the first parity part, and arranging identity matrixes in a full lower triangular form in predetermined blocks from among the blocks classified as the second parity part; and arranging the permutation matrixes in the blocks classified as the information part such that a minimum cycle length is maximized and weight values are irregular on a factor graph of the block LDPC code.

A low density parity check (LDPC) code that is particularly well adapted for hardware implementation of a belief propagation decoder circuit is disclosed. The LDPC code is arranged as a macro matrix (H) whose rows and columns represent block columns and block rows of a corresponding parity check matrix (H_pc). Each non-zero entry corresponds to a permutation matrix, such as a cyclically shifted identity matrix, with the shift corresponding to the position of the permutation matrix entry in the macro matrix. The block columns of the macro matrix are grouped, so that only one column in the macro matrix group contributes to the parity check sum in any given row. The decoder circuitry includes a parity check value estimate memory which may be arranged in banks that can be logically connected in various data widths and depths. A parallel adder generates extrinsic estimates that are applied to parity check update circuitry for generating new parity check value estimates. These parity check value estimates are stored back into the memory, and are forwarded to bit update circuits for updating of probability values for the input nodes. Variations including parallelism, time-sequencing of ultrawide parity check rows, and pairing of circuitry to handle ultrawide code rows, are also disclosed.

Generally, a method and apparatus are provided for computing a matrix inverse square root of a given positive-definite Hermitian matrix, K. The disclosed technique for computing an inverse square root of a matrix may be implemented, for example, by the noise whitener of a MIMO receiver. Conventional noise whitening algorithms whiten a non-white vector, X, by applying a matrix, Q, to X, such that the resulting vector, Y, equal to Q·X, is a white vector. Thus, the noise whitening algorithms attempt to identify a matrix, Q, that when multiplied by the non-white vector, will convert the vector to a white vector. The disclosed iterative algorithm determines the matrix, Q, given the covariance matrix, K. The disclosed matrix inverse square root determination process initially establishes an initial matrix, Q₀, by multiplying an identity matrix by a scalar value and then continues to iterate and compute another value of the matrix, Q_n+1, until a convergence threshold is satisfied. The disclosed iterative algorithm only requires multiplication and addition operations and allows incremental updates when the covariance matrix, K, changes.

The present invention relates to a decoding apparatus and a decoding method for realizing the decoding of LDPC codes, in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. A check matrix of LDPC codes is formed by a combination of a (P×P) unit matrix, a matrix in which one to several 1s of the unit matrix are substituted with 0, a matrix in which they are cyclically shifted, a matrix, which is the sum of two or more of them, and a (P×P) 0-matrix. A check node calculator 313 simultaneously performs p check node calculations. A variable node calculator 319 simultaneously performs p variable node calculations.

The transmit diversity and symbol rate in a wireless mobile system are increased by allocating the complex symbols to be transmitted in accordance with a time-space slot format that incorporates non-orthogonal-based matrices, defined as matrices whose format is such that the product of the matrix and its Hermitian transpose is other than the identity matrix times a real number other than unity. The non-orthogonal-based matrices are indexed by antenna and by symbol period. Copies and complex conjugates (or negative complex conjugates) of the same symbol that are transmitted from different antennas are mutually separated into non-adjacent parts of the slot. Each non-orthogonal-based "space-time" matrix is composed of orthogonal-based matrices, i.e., matrices other than non-orthogonal-based matrices. Preferably, sequences of complex conjugates are time-reversed in the slot.

The invention provides an identity authentication method and system. The method comprises the steps of collecting voice signals, fingerprint image data and face image data of a user; extracting spectrum features of the voice signals to obtain voiceprint feature information; converting the voiceprint feature information, the fingerprint image data and the face image data into a voiceprint matrix, afingerprint image matrix and a face image matrix of preset dimensions; splicing the three matrixes to obtain identity matrix data; inputting the identity matrix data into a preset neural network model to obtain first biological feature data of the user; calculating the similarity between the first biological feature data and second biological feature data of pre-registered users; determining a target user corresponding to the highest similarity; returning a verification result showing that the target user passes the identity authentication if the highest similarity is greater than a preset similarity threshold; and returning the verification result showing that the target user does not pass the identity authentication if the highest similarity is smaller than or equal to the preset similarity threshold.

The present invention relates to a decoding method and a decoding apparatus in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. By using a transformation check matrix obtained by performing one of or both a row permutation and a column permutation on an original check matrix of LDPC (Low Density Parity Check) codes, the LDPC codes are decoded. In this case, by using, as a formation matrix, a P×P unit matrix, a quasi-unit matrix in which one or more is, which are elements of the unit matrix, are substituted with 0, a shift matrix in which the unit matrix or the quasi-unit matrix is cyclically shifted, a sum matrix, which is the sum of two or more of the unit matrix, the quasi-unit matrix, and the shift matrix, and a P×P 0-matrix, the transformation check matrix is represented by a combination of a plurality of the formation matrices. A check node calculator 302 simultaneously performs p check node calculations. A variable node calculator 304 simultaneously performs p variable node calculations.

This invention relates to a method for constructing new non-standard replacement matrix LDPC codes characterizing that under the principle of optimizing the smallest ring circuit, it takes each sub-block as the smallest unit and utilizes a binary chart with weight to determine the position of the sub-block and the deviation of circulation shift: simplifying the binary chart with bit as the unit of the LDPC code to that with a sub-block as the unit based on the property of the matrix of a replacement unit, then applying the traditional PEG algorithm with the bit as the unit to the new chart with the sub-block as the unit to determine the position of every replacement unit matrix of the H matrix and finally utilizing the ring circuit property of the LDPC code to decide the deviation of circular shift of each replacement unit matrix.

The invention provides an encoding method of an LDPC (Low Density Parity Check) code. The encoding method comprises the following steps of: adjusting elements of a modular matrix Hbm by using an expanding factor zf to generate an adjusted modular matrix Hbmf; expanding by using the modular matrix Hbmf to generate a check matrix H, wherein the expanding mode is as follows: sub-matrixes Pi and j in the check matrix H expand according to the value of the modular matrix Hbmf, and each of the sub-matrixes Pi and j is a full zero matrix, a unit matrix or a unit matrix for left and right cyclic shifting according to a line direction; and encoding input information U by using the check matrix H and outputting encoding information V. The invention also provides an encoder of the LDPC code. According to the technical scheme proposed by the invention, through increasing the quantity of zero elements of the modular matrix Hbm, the processing complexity and the implementation complexity of the encoding and the decoding of the LDPC code can be reduced, and the processing speed of the encoding and the coding can be improved.

The invention discloses a low-complexity quick parallel matrix inversion method. The method comprises the following steps that first, a matrix A is given, a matrix E is made to be a unit matrix with the same order as the matrix A, the matrix A and the matrix E form an expanding matrix B, modified Givens rotation (MSGR, Modified Square Givens Rotations) is carried out on the matrix B, an upper triangular matrix U and , wherein according to the define of the matrix U and , an SGR (Squared Givens Rotations) method is used for deforming the QR division of the matrix A according to the equation, and the relation between the QR division and original QR division meets the equations , , , and ; according to the MSRG method, the square root operation in the process of Givens rotation can be omitted while division operation is reduced, and algorithm complexity is obviously reduced; second, a back substitution method is used for working out the inverse matrix U-1 of the upper triangular matrix U; third, matrix inversion is carried out according to the equation . According to the low-complexity quick parallel matrix inversion method, a large amount of division operation and a large amount of square root operation are omitted, algorithm complexity is reduced, and the method can be used for matrix inversion of the fields of wireless communication, signal processing and numerical calculation.

The invention belongs to the communication technology field, particularly relates to a structuring method of a multi-LDPC code. The method comprises steps as follows: the check matrix H of the multi-LDPC code is a partitioned matrix which consists of (m multiplying n) sub-matrixes of H<i, j>, and each sub-matrix H<i, j> is obtained from that a scale factor beta<i, j> epsilon GF(q) is multiplied by a unit matrix of (1 multiplying 1) and then left moved by s<i, j> times according to a line cycle; wherein, GF(q) is a finite field having q elements; the check matrix H of the multi-LDPC code can be divided into two parts, namely, H is equal to (H1H2); wherein, the H2 is a dual partitioned diagonal matrix with a size of m multiplying m and the H1 consists of sub-matrixes left in the H; the H1 corresponds to information symbols and the H2 corresponds to check symbols. In addition, the invention also provides a fast coding method applicable to the invented multi-LDPC code.

The architecture is able to switch to Non-blocking check-node-update (CNU) scheduling architecture which has better performance than blocking CNU scheduling architecture. The architecture uses an Offset Min-Sum with Beta=1 with a clock domain operating at 440 MHz. The constraint macro-matrix is a spare matrix where each “1’ corresponds to a sub-array of a cyclically shifted identity matrix which is a shifted version of an identity matrix. Four core processors are used in the layered architecture where the constraint matrix uses a sub-array of 42 (check nodes)×42 (variable nodes) in the macro-array of 168×672 bits. Pipeline processing is used where the delay for each layer only requires 4 clock cycles.