120 results about "Spurious-free dynamic range" patented technology

In various embodiments, a dynamic range converter includes a plurality of circuits, including at least one configurable circuit that operates based on configuration data. The plurality of circuits include a first color space converter to convert a source color space of a source video having a source dynamic range to nonlinear color space signals. A linearizer configured converts the nonlinear color space signals to linearized color space signals having a mastering dynamic range via a piecewise linear interpolation of a transfer function. A color volume transformer applies dynamic color transform metadata associated with the source video to generate master adjusted color space signals from the linearized color space signals. A delinearizer converts the master adjusted color space signals to nonlinearized color space signals via a piecewise linear interpolation of an inverse transfer function in accordance with a display dynamic range. A second color space converter converts the nonlinearized color space signals to display domain signals. Other embodiments are disclosed.

A randomized thermometer-coding digital-to-analog converter (DAC) for the reduction of harmonic distortion due to non-ideal circuit mismatch is presented. The present invention introduces a new dynamic element matching technique that contains three properties of randomization, consecutive selection and less element switching activity to achieve good spurious-free dynamic range and small maximum output error. The topology uses a bank of 1-bit DAC elements, whose outputs are summed to produce a multi-level analog output. The binary digital input is encoded to be thermometer code. During a randomization period, the thermometer code is barrel-shifted to a specific starting position where the position is generated randomly. Thus, the DAC noise is randomized with less element switching activity and consecutive selection.

The invention provides a bootstrapping sampling switch applied to a high-speed and high-linearity analog-to-digital converter. The bootstrapping sampling switch comprises a clock booster, a grid-source voltage follower, a conduction switch and a charging and discharging enhanced circuit, wherein several times of power voltage are generated by the clock booster and used for charging a capacitor; the grid-source voltage follower connects the capacitor between the grid and the source when the conduction switch is off, so that a relevantly constant grid-source voltage difference under different voltage input is ensured; the charging and discharging enhanced circuit is added in a charging or discharging loop during switching of the switch so as to shorten the off and on time, reduce a parasitic capacitance of the grid of the conduction switch and reduce the loss of the storage charge of the capacitor; the use of a high-voltage metal oxide semiconductor (MOS) tube is not needed; meanwhile, high-linearity sampling is realized (the sampling rate is more than 1 KMHz under 65-nano complementary metal-oxide-semiconductor (CMOS) technology and a stray-free dynamic range more than 95 decibels can be obtained). A complicated logic control circuit is absent in the structure, so the area of a chip cannot be increased; moreover, a requirement of the clock buffer is not needed to be enhanced.

The invention provides a successive approximation type analog-to-digital converter and a calibration method. The successive approximation type analog-to-digital converter comprises a sampling / holdingcircuit, a digital-to-analog converter, a comparator, a successive approximation logic circuit, a clock generation circuit and a digital pseudo-random signal generator. An analog input signal is connected to the sampling / holding circuit. Positive and negative input ends of the comparator are connected with the digital-analog converter and the sampling / holding circuit respectively, and the output end of the comparator is connected with the successive approximation logic circuit; the successive approximation logic circuit and the digital pseudo-random signal generator are connected to the inputof the adder, and the output of the adder is connected with the digital-to-analog converter; the successive approximation logic circuit and the digital pseudo-random signal generator are connected tothe input of a subtracter, and the output of the subtracter is a final output result; and the clock generation circuit is respectively connected with the comparator and the successive approximation logic circuit. Harmonic energy is reduced, the spurious-free dynamic range of the ADC is improved, and the linearity of the core ADC is effectively improved.

A randomized thermometer-coding digital-to-analog converter (DAC) for the reduction of harmonic distortion due to non-ideal circuit mismatch is presented. The present invention introduces a new dynamic element matching technique that contains three properties of randomization, consecutive selection and less element switching activity to achieve good spurious-free dynamic range and small maximum output error. The topology uses a bank of 1-bit DAC elements, whose outputs are summed to produce a multi-level analog output. The binary digital input is encoded to be thermometer code. During a randomization period, the thermometer code is barrel-shifted to a specific starting position where the position is generated randomly. Thus, the DAC noise is randomized with less element switching activity and consecutive selection.

A successive approximation register (SAR) analog-digital converter (ADC) and a method of driving the same are provided. The SAR ADC includes a first converting unit including a bit capacitor array corresponding to the number of bits and a correction capacitor array, a comparator outputting a high or low voltage corresponding to each capacitor according to an output voltage of the converting unit, and a correction unit correcting the output of the bit capacitor according to the output of the correction capacitor array among the high or low output of the comparator. Therefore, two bits having the same capacitance as a least significant bit (LSB) enable a digital output error to be corrected, so that a spurious free dynamic range (SFDR) of the signal converter is increased, and a signal to noise and distortion ratio (SNDR) of an output signal is improved.

The invention relates to an open loop amplifier with stable output common-mode voltage. The open loop amplifier comprises a main amplifier unit and an auxiliary amplifier unit. Compared with a conventional negative feedback amplifier with stable output common-mode voltage, the open loop amplifier has the beneficial effects that the differential output common-mode voltage of the main amplifier unit under an open loop structure is stable; the differential output end of the main amplifier unit does not adopt a common-mode feedback circuit, so that the output load is lowered, the working conversion speed of the amplifier is increased, and the frequency of an analog input signal can exceed 1GHz when the dynamic indicator SFDR (Spurious Free Dynamic Range) of the main amplifier unit exceeds 70dB. The circuit provided by the invention is applied to the field of ultrahigh-speed sampling / retaining circuits in low-voltage CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process circuits with a high dynamic performance requirement.

The invention relates to a high-precision and low-distortion digital-analog converter which comprises an analog adder / subtractor, first and second analog integrators, an analog adder, an analog-digital converter, first, second and fourth gain amplification stages, an analog gain stage and a feedback gain amplification stage. A signal output end OUTPUT is connected with an output end of the analog-digital converter, a second-order DEM (dynamic element matching) module is arranged between the analog-digital converter and the analog adder / subtractor, an input end of the second-order DEM module is connected with the output end of the analog-digital converter, and an output end of the second-order DEM module is connected with an input end of the analog adder / subtractor by a digital-analog converter. The high-precision and low-distortion digital-analog converter has the advantages that owing to a feedback factor adding mode, zero points are imported into noise transfer functions, accordingly, noise power in signal base bands can be reduced, the signal-to-noise ratio of the high-precision and low-distortion digital-analog converter can be increased, and the system precision of the high-precision and low-distortion digital-analog converter can be improved; second-order suppression can be carried out on mismatched noise by the aid of second-order sigma-delta DEM technologies, accordingly, the signal-to-noise distortion ratio of the integral sigma-delta analog-digital converter can be increased, and the spurious-free dynamic range of the integral sigma-delta analog-digital converter can be expanded.

A digital-to-analog converter (DAC) error suppression arrangement suppresses DAC error arising from mismatched elements contained in a DAC (640 and / or 645) that is part of a modulator (FIG. 6). A low pass averaging (LPA) index decoder 650 controls a shifting arrangement 635 to shift a digital word T2 derived from modulator output Y so that the DAC error distribution constitutes a low pass profile (FIG. 5). Thus, DAC error is suppressed at higher frequencies (close to half the sampling rate), thereby providing improved spurious free dynamic range (SFDR). The LPA index decoder 650 causes the shifting arrangement 635 to shift the digital word T2 using only a single pointer per clock cycle.