Background calibration method for capacitance mismatch and interstage gain error of pipelined SAR ADC (Synthetic Aperture Radar Analog-to-Digital Converter)

Abstract

The invention discloses a background calibration method for correcting capacitance mismatch and an interstage gain error in a pipelined SAR ADC (Synthetic Aperture Radar Analog-to-Digital Converter),which comprises the following steps of: injecting a pseudo random sequence PN (Pseudo-Noise) signal into a background, extracting the gain error of the capacitance mismatch and the interstage operational amplifier, and then correcting the gain error by a digital calibration engine. Meanwhile, the invention further provides a noise quantizer technology. During the first-stage SAR conversion, the inter-stage operational amplifier is multiplexed into an additional comparator, the two comparators compare the same input signal, and the comparison result is used for detecting whether the margin voltage is near the threshold of the comparator or not, thereby deciding whether to inject a pseudo random sequence PN signal or not. According to the method, capacitor mismatch and gain errors in the pipelined SAR ADC can be corrected without an additional analog circuit and time sequence overhead, harmonic components in a signal band can be effectively reduced, the signal-to-noise ratio is obviouslyimproved, and the spurious-free dynamic range is obviously enlarged.

Description

technical field [0001] The invention relates to the technical field of high-precision analog-to-digital converters, in particular to a background calibration method for correcting capacitance mismatch and inter-stage gain errors in a pipelined SARADC. Background technique [0002] Pipelined Successive Approximation Register Digital to Analog Converter (Pipelined Successive Approximation Register Digital to Analog Converter, hereinafter referred to as pipelined SAR ADC) is actually an effective combination of pipelined ADC and SAR ADC. mechanism combined to achieve high energy efficiency and high-speed performance at the same time. However, the resolution of pipelined SAR ADCs is limited by capacitance mismatch and inter-stage gain errors. To improve resolution, jitter-based calibration is widely used in various ADCs to correct capacitance mismatch or gain error, but it requires additional hardware overhead or complex switching operations. Data-weighted averaging techniques...

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Problems solved by technology

But in this paper, the additional time-domain proximity detector will add additional analog circuits and circuit complexity. At the same time, the injection of PN will consume the inter-stage redundancy of the pipelined SAR ADC, which may saturate the second-stage SAR ADC.

[0004] At the 2017 IEEE ISSCC meeting, the literature [C.Liu and M.Huang.:'A 0.46mW 5MHz-BW79.7dB-SNDR noise shaping SAR ADC with dynamic-amplifier-based FIR-IIRfilter', International Solid-State Circuits Conference , San Francisco, CA, 2017, pp.466-467] Using data weighted average technology to disperse the harmonics caused by capacitor mismatch, but data weighted average technology requires a capacitor array with temperature code encoding and a binary to temperature code circuit, which is undoubtedly Increase the area power consumption and circuit complexity of the system, and also increase the delay of digital logic

However, the gain error shaping technology requires an additional digital-to-analog converter, and the gain error shaping technology can only suppress the gain error, and has no shaping effect on the capacitance mismatch

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