Digital background calibration method for capacitor mismatch and gain errors of pipelined SAR ADC

Abstract

The invention discloses a digital background calibration method for capacitor mismatch and gain errors of a pipelined SAR ADC, and belongs to the technical field of high-precision analog-to-digital converters. The method comprises: firstly, detecting a conversion result of a first stage by a digital detector; then, switching a first-stage switch array according to the detection result and a pseudo random number so as to realize random injection. In order not to increase the output swing of an amplifier and avoid the saturation of a second-stage SAR ADC, only the mismatch value of the capacitor, rather than a single capacitance value, is injected into the first-stage margin voltage, so that the injection amplitude can be effectively reduced. By performing the calibration in the background,the actual capacitance mismatch size and interstage gain value can be obtained. Simulation results show that after correction, the signal-to-noise distortion ratio is increased from 42.4 dB to 59.3 dB, and the spurious-free dynamic range is increased from 50.6 dB to 79.1 dB.

Description

technical field [0001] The invention belongs to the technical field of high-precision analog-to-digital converters, and relates to a brand-new digital background calibration algorithm, in particular to a digital background calibration method for pipelined SAR ADC capacitance mismatch and gain error. Background technique [0002] Due to the inherent serial operation of the successive approximation register analog-to-digital converter (Successive Approximation Register Analogue to Digital Converter, hereinafter referred to as SAR ADC), its conversion speed is usually limited to about 100M / s in 10bit or higher resolution applications . A method for overcoming the speed bottleneck is to introduce the working mechanism of a Pipelined Analogue to Digital Converter (hereinafter referred to as PipelinedADC) into the conversion of the SAR ADC. However, in the pipelined SAR ADC, capacitance mismatch and inter-stage gain error are important factors affecting its dynamic performance. ...

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Problems solved by technology

But they either need complex logic to detect whether the jitter signal is injected, or the swing and linearity requirements of the op amp will be increased due to the injection of the jitter signal

In reference [R.Xu, B.Liu and J.Yuan.:'Digitally Calibrated 768-kS / s 10-b Minimum-Size SAR ADC Array With Dithering', J.Solid-State Circuits,2012,47,(9) , pp. 2129–2140], although no additional circuit is required to detect the injection condition of the jitter signal, but this calibration method needs to double the ADC conversion speed when it runs in the background, obviously this shortcoming greatly reduces the calibration. Application Scenario

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