Background calibration method based on related SAR ADC capacitor mismatch errors

A technology of capacitance mismatch and calibration method, which is applied in the direction of analog/digital conversion calibration/test, electrical components, electrical signal transmission system, etc., can solve the problems of limited application, and achieve the goal of improving signal-to-noise ratio and spurious-free dynamic range Effect

Active Publication Date: 2020-11-06
SOUTHEAST UNIV
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The advantage of this correlation-based calibration method is that it can converge quickly, but when running i

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  • Background calibration method based on related SAR ADC capacitor mismatch errors
  • Background calibration method based on related SAR ADC capacitor mismatch errors
  • Background calibration method based on related SAR ADC capacitor mismatch errors

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[0026] Below in conjunction with accompanying drawing, technical scheme of the present invention is described in further detail:

[0027] The present invention proposes a background calibration method based on the relative SAR ADC capacitance mismatch error. Figure 1a and Figure 1b Shown is the structural block diagram and timing diagram of the SAR ADC proposed by the present invention. Improvements are made on the basis of the standard 10bit SAR ADC structure. The block diagram mainly includes a 5bit coarse SAR ADC, a skip control logic and a 10bit fine SAR ADC. The DAC in the fine SAR ADC is divided into a 5-bit MSB segment and a 7-bit LSB segment. 2-bit redundancy is added to the LSB segment to tolerate the gain error and comparator offset voltage between the coarse SAR ADC and the fine SAR ADC. Figure 1a and Figure 1b shown, the capacitor C R6 and C R11 It is a 2bit redundant capacitor, which provides redundant ranges of ±16LSB and ±1LSB respectively. In addition, ...

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Abstract

The invention discloses a background calibration method based on related SAR ADC capacitor mismatch errors. Pseudo-random signal PN is injected into the margin voltage by using a detection skip algorithm and an alignment switching technology, and then the digital signal and the pseudo-random signal PN are subjected to related operation at the background, so that the capacitor mismatch error can beextracted. Because the weight error injected into the margin voltage is very small relative to the total capacitance, the margin increment caused by injection can be ignored. Therefore, the calibration algorithm does not need to increase the condition of extra circuit detection injection, and can also minimize the overhead of a redundancy range. Simulation results show that after correction, thesignal-to-noise distortion ratio is increased from 35.9 dB to 61.1 dB, and the spurious-free dynamic range is increased from 41.2 dB to 79.3 dB.

Description

technical field [0001] The invention relates to a brand-new digital background calibration algorithm, which is mainly used for calibrating capacitance mismatch errors in SAR ADCs, and belongs to the technical field of high-precision analog-to-digital converters. Background technique [0002] Due to the simple quantization structure and the high dependency of the digital circuit, the Successive Approximation Register Analogue to Digital Converter (SARADC for short) exhibits superior performance in low-power electronic applications. SAR ADC can use low-power comparator junction and majority voting technology to reduce comparator power consumption, and can also use subranging structure combined with check skipping algorithm to reduce capacitor switching energy. Among them, the subranging structure combined with the check skipping algorithm was first published in the 2014 IEEE ISSCC conference [Tai,H.,Hu,Y.,Chen,H.,and Chen,H.:'11.2A 0.85fJ / conversion-step 10b 200kS / ssubranging...

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Application Information

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IPC IPC(8): H03M1/10H03M1/08H03M1/38
CPCH03M1/1009H03M1/08H03M1/38
Inventor 吴建辉张力振冯金宣孙志伟李红
Owner SOUTHEAST UNIV
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