Background calibration method based on related SAR ADC capacitor mismatch errors
A technology of capacitance mismatch and calibration method, which is applied in the direction of analog/digital conversion calibration/test, electrical components, electrical signal transmission system, etc., can solve the problems of limited application, and achieve the goal of improving signal-to-noise ratio and spurious-free dynamic range Effect
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[0026] Below in conjunction with accompanying drawing, technical scheme of the present invention is described in further detail:
[0027] The present invention proposes a background calibration method based on the relative SAR ADC capacitance mismatch error. Figure 1a and Figure 1b Shown is the structural block diagram and timing diagram of the SAR ADC proposed by the present invention. Improvements are made on the basis of the standard 10bit SAR ADC structure. The block diagram mainly includes a 5bit coarse SAR ADC, a skip control logic and a 10bit fine SAR ADC. The DAC in the fine SAR ADC is divided into a 5-bit MSB segment and a 7-bit LSB segment. 2-bit redundancy is added to the LSB segment to tolerate the gain error and comparator offset voltage between the coarse SAR ADC and the fine SAR ADC. Figure 1a and Figure 1b shown, the capacitor C R6 and C R11 It is a 2bit redundant capacitor, which provides redundant ranges of ±16LSB and ±1LSB respectively. In addition, ...
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