50% duty ratio clock generation circuit

Abstract

The invention provides a 50% duty ratio clock generation circuit, and relates to the field of digital-analog hybrid integrated circuit design. The circuit comprises a low-noise amplification buffer circuit and a duty ratio modulation circuit. The low-noise amplification buffer circuit is used for amplifying an externally inputted differential clock signal so that a single-end clock signal is generated and outputted to the duty ratio modulation circuit. The duty ratio modulation circuit is used for modulating duty ratio of the single-end clock signal so that a clock single with duty ratio of 50% is generated. The differential clock signal is converted into the single-end clock signal by the circuit via the low-noise amplification buffer circuit, duty ratio of the single-end clock signal is modulated and clock single with duty ratio of 50% is generated so that design difficulty and power consumption of a sampling and holding circuit in an analog-to-digital conversion circuit are reduced, and signal-to-noise ratio (SNR) and a spurious free dynamic range (SFDR) of an analog-to-digital conversion quantizer are enhanced.

Description

technical field [0001] The invention relates to the field of digital-analog hybrid integrated circuit design, in particular to a 50% duty ratio clock generation circuit. Background technique [0002] With the continuous development and shrinking of complementary metal oxide semiconductor (CMOS) technology, people's demand for high-speed, high-precision and high-integration integrated circuits is growing rapidly. However, the synchronization between IC modules becomes one of the bottlenecks in high-performance systems. In these systems, the signal-to-noise ratio is one of the important measures of system performance. The noise in the clock circuit will be transmitted to the whole system, thereby affecting the signal-to-noise ratio of the whole system, and even affecting the performance of the whole system. At the same time, for a high-performance analog-to-digital converter, the settling time of the quantizer is more demanding. Since the circuit in the quantizer works in tw...

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Problems solved by technology

At the same time, due to the existence of parasitic capacitance, it takes a certain amount of time for the circuit to generate UP and DOWN signals, which results in that when the input phase difference is less than a certain value, the charge pump cannot inject current, then the entire loop gain is zero, and the output phase cannot Locking, the very small phase difference between CLKIN and CLKOUT cannot be recognized, that is to say, there will be a dead zone near the phase equal to zero between the loop filter and the charge pump, which will cause phase jitter and cause the output clock Signal Duty Cycle Periodic Error

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