High spurious-free-dynamic-range (SFDR) multichannel time staggering successive approximation type analog to digital converter

Abstract

The invention belongs to the technical field of integration circuits and particularly relates to a high spurious-free-dynamic-range (SFDR) multichannel time staggering successive approximation (SAR) type analog to digital converter. A capacitor array for sampling and quantifying at the front end of each channel of the conventional multichannel time staggering SARADC is often relatively independent and fixed; and the own capacitor array of each channel at the front end is dismantled into a number of equal modules so as to form a 'capacitance pool'. Before sampling, the capacitance pool is randomly distributed to each channel, so a fixed error of each channel is reduced and randomized then; from an energy spectrum, energy of a harmonic component is changed into noise which is normalized to a noise base; therefore, the nonlinearity caused by capacitance mismatch is improved effectively.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a multi-channel successive approximation analog-to-digital converter. Background technique [0002] The structure diagram of a common multi-channel successive approximation analog-to-digital converter is as follows: figure 1 As shown, in order to facilitate the analysis, the equivalent circuit of each channel is shown as figure 2 shown. It is mainly composed of track and hold circuit, reference voltage, DAC composed of capacitor array, digital control unit with shift register as the core, comparator and switch array. Under normal circumstances, the conversion process is as follows image 3 shown. First the digital control logic unit ( figure 2 The SAR Logic in the control sample and hold unit sampling, and then control the highest bit of the DAC array to connect to V ref ( image 3 shown), the output V ref / 2, the comparator will input V in Comp...

AI Technical Summary

Problems solved by technology

If the capacitors do not match, it will cause quantization errors, and the output digital code becomes 000101, see Figure 4 shown

Therefore, when the capacitance is not matched, different errors are introduced between different channels, and when passing through the overall encoding output module (see Figure 1 ), will affect the overall linearity

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