480 results about "Time interleaved" patented technology

A transmission method of a digital broadcast which is compatible with the DVB-T terrestrial digital broadcast system in Europe and saves a battery in a mobile terminal is provided. Superframes in DVB-T are divided into units each including plural symbols so that an integer number of TS packets can be carried in each slot. At least one slot is used to transmit one service. Energy dispersion, Reed-Solomon coding, byte interleaving, convolutional coding, and time interleaving are applied to each service. When services for mobile terminal reception and services for fixed terminals are transmitted as the provided services, null packets may be transmitted before and after the slot carrying the mobile receiver service so that the fixed reception service and the mobile reception services are not mixed. If the fixed terminal handles TS packets of the mobile reception service as error packets, it could have no problem in reception.

Samples of a scene are acquired in synchronization with finely interleaved varying conditions such as lighting, aperture, focal length, and so forth. A time-varying sample at each pixel for each condition is reconstructed. Time multiplexed interleaving allows for real-time, live applications, while handling motion blur naturally. Effects such as real-time video relighting of a scene is possible. Time interleaved exposures also allow segmentation of a scene, and allows for constrained special effects such as triangulation matting using a multi-color interleaved chroma key.

In an aircraft galley, a power network distributes power from a source to electrical consuming devices (oven, water boiler, coffee machine, trash compactor, etc.). A control unit is connected to and can individually address each of the devices via a databus. The control unit compares the actual existing power consumption to a prescribed maximum value. If the actual consumption reaches the maximum value, the control unit calls up a power reduction procedure from a catalog in a database, and provides corresponding control signals to one or more of the devices to reduce the power consumption below the maximum value. The individual devices receive power in a time-sharing, power-sharing, or time-staggered manner. An intelligent distribution of available power resources avoids power overloads, and allows optimal utilization of all galley devices without limiting the normal catering process.

In a multi-channel video transmission system in which channel video segments are operated on by corresponding channel video encoders to encode the video segments into frames organized into groups of defined frame types, an apparatus and method to cause a temporal staggering for the processing of a specific frame type among the various channels. In one preferred embodiment, the apparatus includes a frame counter to synchronize reset signals associated with the corresponding channel video encoders and a means for providing a timing offset to channel video encoders corresponding to a selected frame stagger for a particular corresponding channel.

A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

A high-speed sampling system and an analog to digital converter are disclosed. One embodiment of a method of sampling a signal includes receiving an analog signal and generating first samples at a rate of Fs, and generating second sub-samples from the first samples at a rate of Fs/N and having a relative phase of approximately (360/N)*(i−1) degrees, where i varies from 1 to N. In a first embodiment, at most two second sub-samplers are tracking the output of the first sampler at any point in time. In a second embodiment, only one of the N second sub-samplers are tracking the output of the first sampler at any point in time. A third embodiment further includes generating third samples from the second samples at a rate of Fs/N, and having a relative phase of approximately ((360/N)*(i−1)+180) degrees. A method of interleaved analog to digital converting includes corresponding time interleaved ADCs receiving the third samples.

Compression of signal samples output from a parallel, time-interleaved analog to digital converter (TIADC) for a baseband signal, includes calculating first or higher order differences of consecutive signal samples followed by lossless or lossy encoding of the difference samples to produce compressed samples. Compression of a TIADC output signal with a nonzero center frequency, includes calculating sums or differences of pairs of signal samples separated by an appropriate number of sampling intervals followed by lossless or lossy encoding. The sums or differences of the signal samples have lower magnitudes than the original samples, allowing more efficient compression. Lossy compression alternatives produce compressed data with a fixed bit rate or with a fixed quality in the decompressed samples. Alternatives for lossy compression include attenuating the analog signal before sampling by the TIADC, applying bit shifters or multipliers after sampling to reduce the magnitudes of the signal samples, and lossy encoding.

The invention discloses a self-adoptive correcting device of mismatch error of time-interleaved analog-digital converter, comprising an M channel TIADC, a signal recombination, a digital reference signal memorizer, a simulated reference signal generator, a self-adaptive reconstruction filter bank, a clock generation circuit and a subtraction device. Signals after passages are reconstructed are used to correct each passage instead of single correction on each passage, thereby solving the problem that when an input signal bandwidth is larger than the Nyquist frequency of each passage ADC, the time error can not be corrected due to aliasing. Each self-adoptive reconstruction filter is divided into a plurality of sub-filters for concurrent working, thereby not improving the requirement of thetreatment speed for a self-adoptive correcting filter while realizing the effect of signal recombination and ensuring the practicability of the hardware of the structure of the invention. A digital reference signal is internally installed in the device and is taken as a target to carry out the self-adoptive correction, pre-measuring or calculating a passage mismatch error is not needed, and the source of the error is not needed to be discriminated so that various mismatch errors can be corrected.

The invention discloses a high-speed high-accuracy recorder and a designing method thereof. The high-speed high-accuracy recorder comprises a signal conditioning module, four analogue-to-digital converter (ADC) modules, four first in first out (FIFO) modules, two synchronous dynamic random access memory (SDRAM) modules, a client-server architecture control module, a synchronous coherent clock module, a high-accuracy reference voltage source module and the like, wherein the client-server architecture control module consists of an advanced RISC machine (ARM) unit and a field programmable gate array (FPGA) unit; and the synchronous coherent clock module takes a clock chip as a core. The recorder finishes the operations of 'time-interleaved' sampling, encapsulation, caching, transmission, decapsulation combination, correction, storage, uploading and the like concurrently under the control of a concurrent time sequence logic, corrects sampling data based on an inter-ADC channel mismatchingautomatic-correction polynomial to reduce gain mismatching and offset/zero mismatching among ADC channels, reduces time mismatching among the ADC channels by using a synchronous coherent clock and a serpentine curve wire-length fine-adjustment technology, and solves the problems of associated global errors produced by data loss in the high-speed 'time-interleaved' sampling by using a high-order matching technology in which the encapsulation is performed by additional timestamp sequence numbers.

A system and method are provided for adaptive self-calibration to remove sample timing error in time-interleaved ADC of an analog signal. A plurality of ADC channels recursively sample the analog signal within a series of sample segments according to a predetermined sampling clock to generate a time-interleaved series of output samples. A timing skew detection unit is coupled to the ADC channels, which generates for each sample segment a timing skew factor indicative of sampling clock misalignment within the sample segment. Each timing skew factor is generated based adaptively on the output samples for a selective combination of segments including at least one preceding and at least one succeeding sample segment. A plurality of timing control units respectively coupled to the ADC channels adjust time delays for the sampling clock within respective sample segments responsive to the timing skew factors, thereby substantially aligning the sample segments with the sampling clock.

The invention provides a multi-channel time-interleaved analog-digital converter. The multi-channel time-interleaved analog-digital converter is characterized in that a clock generation circuit generates a work clock for the converter; an ADC channel set including M ADC channels is configured into a time-interleaved structure; the ADC channels operate in turns in a time division multiplexing under control of the clock generation circuit, a high-speed analog input signal is converted into M low-speed digital output signals, and M is an integer not smaller than 2; a channel mismatch detection circuit detects timing sequence mismatch errors of signals output by the M ADC channel, in real time, so that a timing sequence mismatch parameter of each ADC channel relative to a reference ADC channel is acquired; a signal compensation and reconstruction circuit compensates and reconstructs the digital output signals output by the ADC channel set according to the timing sequence mismatch errors that the channel mismatch detection circuit detects; a signal combiner circuit combines the M low-speed output signals subjected to channel compensation and generated by the signal compensation and reconstruction circuit, and finally a high-speed digital output signal is obtained.

A method includes determining a value representative of an overall quality of a set of channels and transmitting during a reporting interval an indication of the determined value. The method also includes determining at least one additional value representative of a quality of a subset of the set of channels, and transmitting in at least one subsequent reporting interval an indication of the at least one additional value. Another method includes receiving during a reporting interval an indication of a value representative of an overall quality of a set of channels and receiving during at least one subsequent reporting interval an indication of at least one additional value representative of a quality of a subset of the set of channels. The method further includes, using the values, scheduling resources associated with the channels in the set, and transmitting an indication of the scheduled resources.

An apparatus and method for high-speed analog to digital conversion are disclosed. An ADC system includes a plurality of N/2 sub-ADCs, each sub-ADC receiving an analog signal and a clock signal and generating two digital samples at a rate of Fs/N. The two digital samples are generated with approximately 180 degree phase relationship relative to a frequency of Fs/N. The plurality of N/2 sub-ADCs of the time-interleaved ADC system, generate combined output samples at a rate of Fs. An ADC method includes a plurality of N/2 sub-ADCs receiving the analog signal, clocking each sub-ADC at a rate of FS/N. Each sub-ADC generates two digital samples at a rate of FS/(2N), the two digital samples being generated with approximately 180 degree phase relationship relative to a frequency of Fs/N. Outputs of the sub-ADCs are combined to generate digital samples at a rate of Fs.

A system and method for providing faster tuning into a chosen program in a time-sliced multicast and/or broadcast transmission environment. Multimedia data of the same source material but of different transmission and presentation characteristics are coded and compressed. According to various embodiments, simulcast streams of a program are time-sliced, placed maximally apart from each other in terms of transmission time, and sent over the channel.