34results about How to "Reduce hardware resource consumption" patented technology

A method for adjusting image is applied to an image output device. According to the method, the image output device firstly obtains a current image frame including plural pixels, and analyzes an intensity of an input image signal value of each pixel. The image output device defines each pixel having the input image signal value being smaller than a critical value as a dark pixel, and counts a number of the dark pixels to obtain a ratio of the dark pixels among all the pixels to serve as a dark pixel ratio. The image output device determines an image adjusting curve equation according to the dark pixel ratio, substitutes the input image signal values to the image adjusting curve equation, and obtains output image signal values of the pixels. Finally, the image output device combines all the output image signal values to obtain a final output image frame.

A parallel synchronous scaling engine for multi-view 3D display and a method thereof are provided, wherein selection and combination calculation are provided to an interpolation pixel window, then interpolation calculation is provided to a combined interpolation pixel window of a combined view field, calculation results are directly displayed on a display terminal. That is to say, interpolation is originally provided before stereoscopic pixel rearrangement, which is now improved, in such a manner that screening and combination of pixel points is provided before interpolation calculation. According to the present invention, computation and memory resource is greatly saved. The method is suitable to be implemented by hardware, for satisfying various numbers of viewpoints and interpolation algorithm, and being compatible with multi-view 3D display with the integrated and floating-point pixel arrangement, wherein the computation resource does not need to be increased with increasing of the viewpoints.

The invention discloses an Internet of Things information security chip, comprising a central processing unit, a dynamic memory, a flash memory, an SM2 encryption algorithm unit, an SM3 encryption algorithm unit, an SM4 encryption algorithm unit, an AES encryption algorithm unit, a true random Number generator, physical unclonable function circuit, I2C interface, UART interface, SPI interface, I / O port, JTAG interface and timer; true random number generator is used to generate true random numbers, and physical unclonable function circuit is used for chip authentication and key generation, when the key needs to be used, the true random number generated by the true random number generator is input to the physical unclonable function circuit through the on-chip bus, and the physical unclonable function circuit outputs a unique response sequence, the response sequence is key. The encryption and decryption operation speed of the invention is faster, the consumption of hardware resources and power consumption is less, the key cannot be copied and stolen, and the security and anti-counterfeiting level is higher.

The quantum computer comprises a quasi-one-dimensional layout superconducting quantum bit array, a control circuit and a reading circuit, The superconducting quantum bit array comprises two or more than two net-shaped units which are arranged in a net chain shape. The control circuit is coupled with the superconducting quantum bits through a microwave transmission line and used for controlling thesuperconducting quantum bits in a preset mode; And the reading circuit is coupled to one path of microwave signal line by a coplanar superconducting microwave resonant cavity for reading, is connected with an external circuit, and is used for reading the quantum state of the superconducting quantum bit by adopting a frequency division multiplexing mode. According to the embodiment of the invention, the hardware resource consumption of the quantum computer is reduced.

The invention relates to the technical field of power system simulation, and discloses a hardware-accelerated parallel multi-rate electromagnetic transient real-time simulation method of a converter. Initialized parametric constant admittance model modeling; step 2 realizes the cross-platform decoupling of the converter electrical system and control system solution process; step 3 pre-stores the converter model matrix in FPGA; step 4 is on the host computer Start the parallel simulation and predict the switch state at the next big step; step 5, the FPGA side analyzes the switching state calculation result of the host computer side and solves the electrical state at the current moment in parallel with step 4; step 6, the host computer side reads the FPGA side. The electrical state solves the results and updates the simulation time. The invention is applied to the FPGA-based hardware acceleration simulation scenario of the converter model, effectively reducing the error in the multi-rate decoupling calculation process of the control system and improving the accuracy of real-time simulation.

The invention discloses a high-energy-efficiency high-speed parallel LDPC encoding method and an encoder. The encoding method includes: dividing the input serial or parallel information sequence into multiple sections according to the size of the quasi-cyclic LDPC code cyclic shift sub-matrix, and converting It is an all-parallel data mode; cyclically shifts the segmented information sequence; selects the information bit at the corresponding position according to the position of the non-zero element in the first column of the cyclically shifted sub-matrix; merges the selected information bits of multiple segments; adopts In the pipeline processing mode, the merged information bits are accumulated by modulo two to obtain the corresponding parity bits; the serial parity bits are converted into a full parallel data mode; and the encoding result is output. According to the positions of the non-zero elements in the generating matrix, the present invention selects the bits of the information sequence first, and then performs the encoding calculation, which can effectively avoid the operation of invalid information bits, reduce the number of operations required for the encoding calculation, and thus significantly reduce the overall cost of the encoder. Hardware resource consumption.

The present invention provides a method and an apparatus for cell search and synchronization for subscriber stations of the Long Term Evolution (LTE) system. The invention uses primary synchronizing signal of primary synchronization code in each frame structure to establish synchronization with the base station when a subscriber station accesses the LTE network. With such synchronization between the subscriber station and the base station, control signals and transmission data may be correctly exchanged between them.

The present invention provides a MAC address learning method and device. The method is applied to a TRILL network. The TRILL network includes at least two areas. The RB equipment of the convergence layer in the TRILL network belongs to all areas in the at least two areas. The access layer in the TRILL network The RB devices in the TRILL network belong to one of at least two areas, and the RB devices in the TRILL network are all enabled with ESADI. The method includes: the RB device at the access layer receives the message sent by the local host; the RB device at the access layer learns the message The source MAC address of the document, generate the corresponding MAC entry; notify the source MAC address to other RB devices in the area to which the RB device of the access layer belongs, so that other RB devices in the area can learn the source MAC address and generate the corresponding MAC table item. Therefore, the present invention can save the MAC address space of the RB device at the access layer, and reduce the hardware resource consumption of the RB device at the access layer.