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A high-energy-efficiency high-speed parallel ldpc encoding method and encoder

An encoding method and energy-efficient technology, applied in the field of energy-efficient high-speed parallel LDPC encoding methods and encoders, can solve problems such as low throughput, large frame delay, and high resource consumption, so as to reduce hardware resource consumption and simplify implementation methods , the effect of reducing the number of operands

Active Publication Date: 2022-02-18
UNIV OF SCI & TECH BEIJING
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the serial SRAA encoder has a large processing delay and low throughput, and is not suitable for high-speed design; the register used by the parallel SRAA encoder is too large, consumes a lot of resources, and its application is limited
Zhang Zhongming et al. proposed an improvement on the problem of large frame delay in the parallel SRAA structure. Encoding can be performed without completely collecting a frame of data. However, the encoder is limited by the integer factorization of the size of the LDPC code quasi-circular matrix. When When the order is a prime number, this method cannot be used for encoding

Method used

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  • A high-energy-efficiency high-speed parallel ldpc encoding method and encoder
  • A high-energy-efficiency high-speed parallel ldpc encoding method and encoder
  • A high-energy-efficiency high-speed parallel ldpc encoding method and encoder

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Embodiment 1

[0056] Embodiments of the present invention provide a high-speed parallel LDPC coding method with high energy efficiency, such as figure 1 As shown, the method includes the following steps:

[0057] Divide the input serial or parallel information sequence into multiple segments according to the size of the quasi-cyclic LDPC code cyclic shift sub-matrix, and convert it into a full parallel data mode;

[0058] Perform cyclic shift on the segmented information sequence;

[0059] According to the position of the non-zero element in the first column of the cyclic shift sub-matrix, select the information bit of the corresponding position;

[0060] Combining the selected information bits of multiple segments;

[0061] The merged information bits are subjected to modulo two accumulation by means of pipeline processing to obtain the corresponding parity bits;

[0062] Convert serial parity bits to full parallel data mode;

[0063] Output the encoding result.

[0064] According to ...

Embodiment 2

[0088] Correspondingly, the present invention also provides an LDPC encoder based on the above-mentioned high-speed parallel LDPC encoding method with high energy efficiency, such as figure 2 As shown, the encoder includes:

[0089] The data preprocessing module is used to divide the input serial or parallel information sequence into multiple segments according to the size of the cyclic shift sub-matrix in the generation matrix, and convert it into a full parallel data mode;

[0090] Multiple cyclic shift modules are used to cyclically shift the segmented information sequence;

[0091] A plurality of bit selection modules are used to select the information bits at the corresponding positions according to the positions of the non-zero elements in the first column of the cyclic shift sub-matrix;

[0092] Multiple bit merging modules are used to combine the outputs of multiple bit selection modules;

[0093] The pipeline accumulation module is used for adopting the pipeline pr...

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Abstract

The invention discloses a high-energy-efficiency high-speed parallel LDPC encoding method and an encoder. The encoding method includes: dividing the input serial or parallel information sequence into multiple sections according to the size of the quasi-cyclic LDPC code cyclic shift sub-matrix, and converting It is an all-parallel data mode; cyclically shifts the segmented information sequence; selects the information bit at the corresponding position according to the position of the non-zero element in the first column of the cyclically shifted sub-matrix; merges the selected information bits of multiple segments; adopts In the pipeline processing mode, the merged information bits are accumulated by modulo two to obtain the corresponding parity bits; the serial parity bits are converted into a full parallel data mode; and the encoding result is output. According to the positions of the non-zero elements in the generating matrix, the present invention selects the bits of the information sequence first, and then performs the encoding calculation, which can effectively avoid the operation of invalid information bits, reduce the number of operations required for the encoding calculation, and thus significantly reduce the overall cost of the encoder. Hardware resource consumption.

Description

technical field [0001] The invention relates to the technical fields of satellite ultra-high-speed information transmission and channel coding, in particular to an energy-efficient high-speed parallel LDPC coding method and a coder. Background technique [0002] With the rapid development of technologies such as space-based information ports, satellite Internet, and distributed constellations, the demand for inter-satellite and satellite-to-ground data transmission has risen sharply. The direct contradiction between limited space communication load resources and high-speed and large-capacity communication requirements has become increasingly prominent. How to carry out research on high-performance signal processing theory and implementation technology under the premise of strict constraints on platform resources, volume, and power consumption has important application value . [0003] Low-density parity-check (LDPC, low density parity check) codes have error correction capa...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/11
CPCH03M13/116
Inventor 李林涛罗裕全戴晓明
Owner UNIV OF SCI & TECH BEIJING
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