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CPLD/FPGA-based clock frequency division module design method

A technology of clock frequency division and module design, applied in the field of frequency division, can solve the problems of high resource consumption, odd frequency division not 50% duty cycle, etc., to achieve the effect of less hardware resource consumption, flexible cutting, and fast update speed

Inactive Publication Date: 2018-01-09
ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] For above-mentioned defect, the object of the present invention is to provide a kind of clock frequency division module design method based on CPLD / FPGA, in order to solve the non-50% duty ratio of instantiation PLL IP core hardware resource consumption in CPLD / FPGA question

Method used

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  • CPLD/FPGA-based clock frequency division module design method
  • CPLD/FPGA-based clock frequency division module design method
  • CPLD/FPGA-based clock frequency division module design method

Examples

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Effect test

Embodiment 1

[0030] Such as figure 2 As shown, the system clock on the motherboard is used as the reference input clock of the integer frequency division module, and the given module input parameters are used as the frequency division base N of the integer frequency division module according to actual needs. Select an even frequency division module or an odd frequency division module according to the frequency division base N, and at the same time, turn off the other frequency division module, sample and divide the reference input clock to obtain the desired frequency division clock; according to the frequency division base N, select an even number The N-divided clock obtained by the frequency division module or the odd frequency division module is used as an output frequency division clock and as an input clock of other modules.

[0031] Even frequency division module:

[0032] In order to divide the reference clock by even numbers, an even frequency division module is designed, and its...

Embodiment 2

[0036] In order to verify the effectiveness of any integer frequency divider based on CPLD / FPGA, in the ModelSim environment, by giving different frequency division numbers N, the frequency divider is verified. The integer frequency divider realizes 4 (N is an even number) division Frequency simulation results such as Figure 6As shown, the simulation results of frequency division by 5 (N is an odd number) implemented by an integer frequency divider are as follows Figure 7 shown. It can be seen from the simulation results that the present invention is based on CPLD / FPGA oriented to any integer 50% duty ratio frequency frequency clock modular implementation method can output high-quality frequency division clock according to the N value, which verifies that the present invention is oriented to any integer number based on CPLD or FPGA. 50% duty cycle divided clock availability.

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Abstract

The invention discloses a CPLD / FPGA-based clock frequency division module design method. The method comprises the following steps of 1: taking a system clock on a mainboard as a reference input clockof a clock frequency division module, and inputting a frequency division cardinal number N; 2: judging the parity of the frequency division cardinal number N, selectively using an even number frequency division module or a cardinal number frequency division module to perform frequency division, selecting the frequency division module, and turning off the other module; 3: performing sampling and frequency division on the reference input clock to obtain an expected frequency division clock; and 4: outputting the clock. The problems of high consumption of instantiated PLL IP core hardware resources in a CPLD / FPGA and non 50% duty ratio of odd number frequency division are solved.

Description

technical field [0001] The present invention relates to the technical field of frequency division methods, in particular to a design method for clock frequency division modules based on CPLD / FPGA. Background technique [0002] With the development of integrated circuits, the requirements for the clock are getting higher and higher, and the quality of the clock directly affects the performance of the entire system, and even affects the stability of the system. For high-end CPLD / FPGA chips, the clock with the desired frequency can be obtained by instantiating the PLL IP core, but there is a problem of consuming more hardware resources. And for different types of CPLD / FPGA chips, PLL IP cores generally cannot be transplanted. Therefore, it is of great significance to design a frequency divider that is versatile, consumes less hardware resources, and is easy to apply. [0003] In existing designs, most of the PLL IP cores are directly instantiated to obtain the desired frequen...

Claims

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Application Information

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IPC IPC(8): G06F17/50H03L7/18
Inventor 何业缘季冬冬张燕群
Owner ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
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