219 results about "Local circuit" patented technology

A system for controlling electricity consumption of an electricity consumer having a plurality of loads, including: (a) a main central processing unit, connected to a power source, and adapted to receive a signal therefrom; (b) a memory associated with the processing unit; (c) controlled relay assemblies connected to a plurality of loads via local circuit breakers, each assembly including: (i) a relay, responsive to the processing unit; (ii) a current sensor, electrically connected to the relay, the relay and the current sensor being electrically associated with the processing unit, and (iii) an electrical line having a first end connecting the relay assembly to the power source, and having a second end connecting to a local circuit breaker connected to at least one load; wherein each current sensor is adapted to provide, to the processing unit, data pertaining to current drawn via a particular local circuit breaker, and wherein the processing unit is configured to command the relay based on the signal received from the power source, and based on a set of rules provided to the processing unit, the set of rules including load priority information, such that each relay opens or closes in response to the command from the processing unit, so as to shut off or restore power to the electrical line.

An interlocked pipelined CMOS (IPCMOS) family of logic circuits provides extremely high performance pipelined operation and guarantees error free operation where variations in timing are compensated for automatically by the circuits. The IPCMOS logic circuits also provide a standard interface that makes it possible to interface different macro types easily. The IPCMOS logic circuits feature interlocking in both the forward and reverse directions. This "handshaking" guarantees error free timing and makes it possible to eliminate the need for a global clock at the macro level. Timing signals are generated locally at the macro level from the handshaking signals between macros. This makes it possible for the local circuits to deal with global timing variations caused by power supply noise, ACLV, and parameter variations. The macros operate in a pipelined mode with data advancing automatically from macro to macro with the timing controlled by the local handshaking signals. This pipelined operation results in an extremely fast cycle time. Another feature of IPCMOS is that the data inputs to a macro are only sampled when the data is in a valid state. making the concept of a standard macro interface possible. With this standard interface, different logic types such as static and dynamic circuits can be easily interconnected and the concept of reusable macros becomes a reality.

The invention discloses a signal conditioning circuit, a conditioning method thereof and a double sampling retaining circuit. The signal conditioning circuit comprises a first chopping switch, a programmable gain amplifier, a second chopping switch, a double sampling retaining circuit, an analog-to-digital converter, and a digital reduction sampling filter which are connected in sequence. The double sampling retaining circuit samples outputs of the programmable gain amplifier in two-phase positions of a chopping clock, and the results of two samplings are added. and an added output voltage is transmitted to and processed by the analog-to-digital converter, and the digital reduction sampling filter. Since the double sampling retaining circuit is added, the invention avoids the residual and off-tune problem in a chopping amplifier. Meanwhile, the invention facilitates the integration of a single chip, without the need of external filtering capacitor. Furthermore, a novel sequential control reduces the consumption of a digital signal conditioning circuit based on a chopping amplifier.

This invention includes an electronic device that has both electrical contacts for coupling to local, application specific circuitry and contacts for supplying power to another electronic device. The electronic devices may be coupled in series, so as to eliminate the need for bulky, unsightly cables or wires. Since the devices may be coupled in series ad infinitum, the possibility exists that the series combination of devices may draw more power than either a power source can provide or sensitive internal circuitry, like fuses for example, can handle. As such, each electronic device includes a current limiting circuit having a current sense circuit and a switch coupled serially between the input and the output that powers the next electronic device. When the current drawn from the input to the output supplying power for the downstream devices exceeds a predetermined threshold, the switch deactivates the upstream chargers local circuitry. Once the downstream devices have completed their desired activities, the current drawn by the downstream devices will be reduced. When this occurs, the current sense circuits of the upstream devices will detect that the total current drawn has fallen below the predetermined threshold and will once again reactivate their local circuitry. In one embodiment, the electronic devices are desktop battery chargers. By disabling upstream battery chargers while downstream battery chargers complete their charging cycle, the current limiting devices in the upstream battery chargers ensure that fuses disposed within the upstream battery chargers do not blow. A blown fuse in an upstream charger could result in the entire series combination losing power. By including the current limiting circuit of the invention, a user may couple as many series devices together as they want without fear of blowing fuses in the upstream devices.

A local circuit cooperates with a video camera and a trigger signal source such as an existing alarm trigger in an intruder alarm system. A trigger signal causes the local circuit to sample the video camera output and forward one or more images together with date and time information via a public communications channel to a data warehouse where the data is stored in raw, as-received form. The stored data is used to reconstitute one or more images only if necessary, for example if an actual intrusion has occurred.

The invention discloses an experimental system for simulating a single event effect (SEE) of pulse laser based on an optical fiber probe, aiming to reduce beam spot diameter of the pulse laser and realize simulation of the SEE at a single device or a local circuit in a deep sub-micron integrated circuit. The system is composed of a pulse laser, an optical fiber probe and a probe platform, and the aperture of the conical tip of the optical fiber probe is 10nm-1mu m; the input end of the optical fiber probe is connected with the pulse laser, the optical fiber of the optical fiber probe close to the output end is fixed in a probe clip of the probe platform, the output end of the optical fiber probe is contacted with the detected position of an integrated circuit chip, and the optical fiber probe transmits the pulse laser to the output end from the input end; and the integrated circuit chip adopts two modes of being arranged or not arranged in a single event effect detection circuit board. By the invention, pulse laser with the beam spot diameter no more than 1 mu m can be output, thus realizing simulation of the SEE at a single device or a local circuit in a deep sub-micron integrated circuit and lowering the cost.

The invention relates to an on-chip self-triggering single event transient pulse width measurement method and system. The system comprises a combined logic circuit which includes a target circuit module, a gating circuit module, a single event transient pulse width measurement module and a time-delay unit time delay calibration module. The invention provides the on-chip self-triggering single event transient pulse width measurement method and system characterized in that the self-triggering signal generation circuit is simple in structure and no special delay design is required.

The present invention discloses a flat panel display (FPD), a light emitting module for use in the FPD, and an integrated circuit for use in the light emitting module. The light emitting module includes: at least one light emitting device string; and a local circuit for controlling current through the light emitting device string and generating a local feedback signal, wherein the local circuit has a first terminal for receiving power, a second terminal for coupling to the light emitting device string to control the current through the light emitting device string, a third terminal for generating the local feedback signal, and a fourth terminal for coupling to ground. The wiring of the FPD is therefore simplified.

The invention relates to a high-speed yaw scanning control device for testing quality of electron beam current. A complicated programmable logic device is respectively connected with a serial communication circuit and the like; the serial communication circuit is connected with an industrial control computer; two synchronous waveform generating circuits respectively comprise a digital to analog conversion circuit, a low-pass filter circuit, a photoelectric isolation circuit and a power amplifying circuit; two power amplifying circuits are connected with an electromagnetic deflection coil; the frequency of a clock circuit is distributed by the complicated programmable logic device; a clock used for generating various frequencies is respectively used for serial communication, control of a collecting card, and generation of frequency-variable waveforms; the industrial control computer is used for controlling the complicated programmable logic device by the serial communication circuit; the complicated programmable logic device is used for generating the digital quantity of two waveforms under the triggering of the clock circuit; and an amplified signal is used for driving the electromagnetic deflection coil to generate a magnetic field so as to scan the deflection of an electron beam. The device has high control accuracy for scanning the deflection of the electron beam; and a digital circuit can largely enhance the anti-disturbance capability of the device.

The present disclosure provides an integrated circuit. The integrated circuit includes a frequency detector coupled with a logic circuit; a supply voltage regulator coupled with the frequency detector and designed to provide an adaptive voltage supply to the logic circuit based on a frequency error from the frequency detector; and a substrate bias regulator coupled with the frequency detector and designed to provide an adaptive body bias voltage to the logic circuit based on the frequency error.