Double-phase-locked loop circuit and control method thereof

Abstract

The invention discloses a double-phase-locked loop circuit and a control method thereof. The double-phase-locked loop circuit comprises a phase / frequency detector, a charge pump, a frequency adjustment circuit and an N frequency divider. The frequency adjustment circuit comprises a coarse adjustment circuit, a fine adjustment circuit and a current-controlled oscillator, wherein the coarse adjustment circuit is used for coarse adjustment of frequency of output signals of phase-locked loops till approaching a target frequency; the fine adjustment circuit is used for fine adjustment of the frequency of the output signals of the phase-locked loops till the target frequency; and the current-controlled oscillator is coupled with the coarse adjustment circuit and the fine adjustment circuit and used for producing the output signals of the phase-locked loops, wherein the frequency of the output signals is the target frequency. The double-phase-locked loop circuit can effectively achieve the purpose of expanding the frequency adjustment range under the situation of keeping the loop bandwidth of the phase-locked loops smaller, realize the on-chip integration and further reduce the cost and the design complexity of the circuit.

Description

technical field [0001] The present invention relates to a phase-locked loop, and more particularly, to a dual-loop phase-locked loop circuit and a control method thereof. Background technique [0002] The frequency synthesizer composed of the phase-locked loop circuit is an important realization of the clock circuit. It outputs a series of high-stability and high-precision high-frequency clock signals by inputting a high-stability and high-precision low-frequency reference frequency. [0003] figure 1 It is a schematic diagram of the structure of a general phase-locked loop circuit. The working principle of the phase-locked loop is as follows: figure 1 As shown, the phase / frequency detector 3 uses the reference clock signal 1 as a standard and compares its frequency or phase with the feedback signal 2 supplied from the output of the N divider 8. If any phase (frequency) difference is detected within its operating range, an error signal is generated, which is proportional t...

AI Technical Summary

Problems solved by technology

[0007] Although both methods solve the contradiction between wide frequency oscillator and narrow loop bandwidth to a certain extent, each has its own disadvantages

The disadvantage of method 1 is that the filter capacitor is too large to be integrated on-chip, so it must be designed as an off-chip capacitor, which increases the manufacturing cost

The disadvantage of method 2 is that this method cannot track changes in variables such as temperature or process

When variables such as temperature or process change, because the adjustable frequency range of the PLL control loop is small, the circuit needs to periodically switch the digital control circuit to lock the coarse frequency, which increases the complexity of the circuit design, and reduces the accuracy of the circuit

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