160 results about "Current-mode logic" patented technology

A system for a feedback transimpedance amplifier with sub-40 khz low-frequency cutoff is disclosed and may include amplifying electrical signals received via coupling capacitors utilizing a transimpedance amplifier (TIA) having feedback paths comprising source followers and feedback resistors. The feedback paths may be coupled prior to the coupling capacitors at inputs of the TIA. Voltages may be level shifted prior to the coupling capacitors to ensure stable bias conditions for the TIA. The TIA may be integrated in a CMOS chip and the source followers may comprise CMOS transistors. The TIA may receive current-mode logic or voltage signals. The electrical signals may be received from a photodetector, which may comprise a silicon germanium photodiode and may be differentially coupled to the TIA. The chip may comprise a CMOS photonics chip where optical signals for the photodetector in the CMOS photonics chip may be received via one or more optical fibers.

A current mode logic digital circuit is provided comprising a logic circuit component having at least one data input node and at least one output node. A load is coupled between a power supply node and the output node. The load comprises a folded active inductor coupled to the output node.

A method and apparatus for creating high speed logic circuits in a CMOS environment using current steering logic cells with actively-peaked NMOS or PMOS loads and the biasing of these logic cells is disclosed. The logic cells can include, for example, buffers, AND gates, OR gates, flip-flops, and latches. The current steering cells with actively-peaked loads can provide benefits such as reduced power consumption, smaller area, and higher speed performance over conventional devices. This performance boost is preferably achieved using NMOS followers with resistively degenerated gates to create frequency peaked transfer function of current-mode logic cells. These logic cells with actively-peaked loads can advantageously be used in circuits in which relatively good power area and performance are desired for state machine logic, parallel to serial conversions, serial to parallel conversions, and the like.

A multifunctional output driver capable of transmitting signals of different interfaces in different modes is provided, in which first and second current sources are provided, and first to fourth switching devices are coupled between the first and second current sources, and the first and second current source and the first to the fourth switching devices act as a current steering circuit. In a first transmission mode, the first and second switching devices are turned off, and the third and fourth switching devices and the first current source act as a current mode logic circuit to provide an output signal compatible with a first transmission interface according to an input signal from a pre-driver. In a second transmission mode, the current steering circuit outputs an output signal compatible with a second transmission interface according to the input signal from the pre-driver.

An apparatus for use as both an off chip driver (OCD) and an on die termination (ODT) circuits. A preferred embodiment comprises a control circuit (for example, control circuit 305) coupled to a dual function OCD / ODT circuit (for example, OCD / ODT circuit 330) with an enable line coupled to the control circuit. The control circuit may be used to selectively choose OCD and ODT functionality based on a value on the enable line. With the control circuit choosing OCD, the dual function OCD / ODT circuit functions as an OCD circuit, placing signals provided through the control circuit onto a transmission line. With the control circuit choosing ODT, the dual function OCD / ODT circuit becomes terminating resistors for incoming signals on a transmission line. The use of a single circuit for both OCD and ODT functions can save both integrated circuit real-estate and implementation costs due to a reduction in use of circuit elements.

A current mode logic digital circuit is provided comprising a logic circuit component having at least one data input node and at least one output node. A load is coupled between a power supply node and the output node. The load comprises a folded active inductor coupled to the output node.

A combined multiplexer and switched gain circuit (250) that selectively multiplexes differential analog signals from a primary channel (20) and a diversity channel (22) in a diversity receiver system (10) to a single output. The circuit (250) is based on a current mode logic design where a plurality of separate conduction paths (278-284) are provided between a voltage line (266) and a current source (268). An output line (264) of the circuit (250) is coupled to each conduction path (278-284) so that the differential analog signals from the primary channel (20) and the diversity channel (22) can be selectively outputted to the circuit (250). Each conduction path (278-284) includes a gain device, such as degenerative resistor, that provides signal gain or no signal gain for that conduction path (278-284). Control signals are selectively applied to switching devices (310-324) and each conduction path (278-284) so that the conduction path (278-284) can be independently selected to provide the multiplexing.

A serializer includes a first stage configured to convert m-bit-wide parallel data into n-bit-wide parallel data, where n is 2x, m≧2x+y, x is an integer of at least 1, and y is an integer of at least 1, where the first stage includes a memory unit configured to store the m-bit-wide parallel in response to a timing signal and a first multiplexer configured to output the n-bit-wide parallel data in response to a frequency-multiplied derivative of the timing signal, and a current mode logic (CML) multiplexer stage configured to convert the n-bit-wide parallel data into serial data on successive transitions of n phase-shifted versions of the frequency-multiplied derivative of the timing signal.

The invention discloses a differential interface circuit used in the interconnection of long on-chip wires, which is mainly solves the power consumption problem of the interconnection of the long on-chip wires. The structure of the circuit comprises a transmitter, a long interconnection wire and a receiver; wherein, the transmitter consists of an inverter (A1) and an MOS current-mode logic circuit, the transmitter used for converting the full-swing signals on chips into low-swing signals; the receiver is formed by connecting a sensitive amplifier (G), a second inverter (A2) and a third inverter (A3), the receiver is used for restoring the low-swing signals on the longer interconnection wires to the full-swing signals. The differential interface circuit of the invention can effectively reduce the power consumption of interconnection of the long on-chip wires without under the condition of introducing the external reference voltages and can be used in the long wire interconnection of system on chip (SOC) of the integrated circuit design.

An exemplary differential track and hold amplifier includes a track stage including first and second linearized pairs connected in series at their respective inputs and in parallel at their respective outputs. The differential track and hold amplifier also includes a hold stage selectively coupled to the outputs of the first and second linearized pairs. The hold stage includes a unity gain buffer with feedback having a hold capacitor interconnected across its outputs. The differential track and hold amplifier also includes an output buffer coupled to the outputs of the hold stage. An exemplary analog-to-digital converter includes a differential track-and-hold amplifier, a voltage ladder, and a plurality of slices. Each of the slices in turn includes a differential preamplifier coupled to the track-and-hold amplifier and to a corresponding location on the voltage ladder; a current mode logic latch comparator coupled to the differential preamplifier; a large-swing latch coupled to the current mode logic latch comparator; a complementary metal oxide semiconductor latch having a dummy load; a calibration digital to analog converter connected across outputs of the differential preamplifier to inject calibration currents; and a register coupled to the calibration digital to analog converter and storing calibration values for use thereby. The analog-to-digital converter also includes a multiplexer which multiplexes outputs of the complementary metal oxide semiconductor latches down to a predetermined number of outputs.

The invention discloses a phase-switching prescaler based on injection-locking, comprising a multi-phase generator, a multi-channel selector, a true single-phase clock module and a state machine. The multi-phase generator is used for primarily scaling the signal to be scaled and generating N signals with equal phase difference; the multi-channel selector is used for selecting one branch of signal from the N signals with equal phase difference; the true single-phase clock module is used for secondarily scaling the branch of signal selected from the N signals with equal phase difference by the multi-channel selector to obtain the output signal of the phase-switching prescaler; and the state machine is used for transforming the scaling-ratio control signal of the phase-switching prescaler into the control signal of the multi-channel selector. Avoiding adopting the current mode logic, the phase-switching prescaler keeps consuming low power when working at high frequency. An even number of signals with equal phase difference can be generated, thus the scaling-ratio can be selected flexibly when the system is designed. The phase-switching prescaler has better ability of resisting the common-mode noise.

The present invention provides a low swing current mode logic circuit including: a current mode logic block having data inputs and outputs; a pre-charging circuit for pre-charging the outputs; a dynamic current source; an evaluation circuit for evaluating the logic block during an evaluation phase; and, a feedback path arranged between the outputs and the dynamic current source which is responsive to a difference between the outputs. The simplicity of generating the low swing, achieved by the feedback which may be implemented by only two transistors, is in contrast with the complexity introduced by some methods used by other logic styles for achieving low swing.

The invention discloses a current integrating decision feedback equalizer used in a high-speed serial interface, belonging to the field of integrated circuits. The current integrating decision feedback equalizer comprises two branches, wherein each branch is formed as follows: a signal input end orderly passes through an analogue weighting device, a CML(Current-Mode Logic) D trigger and a CML to CMOS (Complementary Metal Oxide Semiconductor) level switching circuit to be connected with a TSPC (True Single Phase Clock) D trigger; the input end of a weighting decision selecting module is respectively connected with the output ends of the two branches and the output ends of the CML to CMOS level switching circuits in the two branches, and the output end of the weighting decision selecting module is respectively connected with the feedback control ends of the analogue weighting devices in the two branches; the output end of one input clock buffer module is respectively connected with the clock control input ends of the CML D triggers and the clock control input ends of the TSPC D triggers in the two branches; and the clock signal of the input clock buffer module is an anti-phase half-speed differential clock signal. The current integrating decision feedback equalizer has the advantages of low error rate, simple structure, low power consumption, and so on.

The invention provides a high-speed current switch driver based on MOS current-mode logic. The driver comprises: a MOS current-mode logic latch circuit for receiving current switch drive signals, and performing latching and amplitude limiting on the current switch drive signals so as to synchronize the current switch drive signals; a MOS current-mode logic current switch for receiving signals processed by the MOS current-mode logic latch circuit, generating current source drive signals with amplitude limited and adjusting crossing points of the current switch drive signals; and a common-source and common-gate current source with a NMOS switch for receiving the current switch drive signals processed by the MOS current-mode logic current switch and outputting low-distortion current signals, thus synchronizing the current switch drive signals and reducing feed-through effect.

The invention discloses a high speed high-oscillation amplitude divide-by-two frequency divider circuit, which belongs to the technical fields of integrated circuit designing and signal processing. Specifically, the circuit mainly comprises two high speed high-oscillation amplitude D triggers which are cascaded. The D trigger of each stage eliminates the bias of a tail current source based on theconventional D trigger having a current-mode logic (CML) structure, and adopts a P-channel metal oxide semiconductor (PMOS) transistor as a load; and simultaneously, a PMOS and N-channel metal oxide semiconductor (NMOS) complementary cross coupling pair structure and the like are adopted by the output stage of the circuit to finally achieve the aims of increasing the oscillation amplitude of an output signal and making the oscillation amplitude of the output signal approximate to full oscillation amplitude under the condition of ensuring the high speed working of the circuit. The circuit not only can directly drive a post circuit, reduces system power consumption to a certain extent, compensates for the shortcomings of a conventional divide-by-two frequency divider, and is suitable for a high speed frequency divider part in a low-power consumption preposed dual-mode prescaler front-end without any additional level conversion amplification circuit.