33 results about "Core level" patented technology

Voltage islands enable a core-level power optimization of ASIC / SoC designs by utilizing a unique supply voltage for each cluster of the design. Creating voltage islands in a chip design for optimizing the overall power consumption consists of generating voltage island partitions, assigning voltage levels and floorplanning. The generation of voltage island partitions and the voltage level assignment are performed simultaneously in a floorplanning context due to the physical constraints involved. This leads to a floorplanning formulation that differs from the conventional floorplanning for ASIC designs. Such a formulation of a physically aware voltage island partitioning and method for performing simultaneous voltage island partitioning, level assignment and floorplanning are described, as are the definition and the solution of floorplanning for voltage island based designs executed under area, power, timing and physical constraints. The physical planning of voltage islands includes: a) characterizing cell clusters in terms of voltages and power consumption values; b) providing a set of cell clusters that belong to a single voltage island Random Logic Macro (RLM); and c) assigning voltages for the voltage island RLMs, all within the context of generating a physically realizable floorplan for the design.

A method and system for digitally controlled multi-frequency clocking are provided. The method includes receiving a system reference oscillator clock frequency at a microprocessor including multiple cores. The system reference oscillator clock frequency provides a reference frequency to a local oscillator. The local oscillator supplies a core clock frequency to at least one of the cores. The method further includes adjusting the local oscillator to output the core clock frequency at a frequency greater than the system reference oscillator clock frequency as a function of digital frequency characteristic data associated with the core or cores. The method supports extendibility to larger systems and may support enhanced power management through frequency adjustments at the core level.

In the static noise check of the LSI hierarchical design, in order to reduce the data volume of the common parts and load of the design operation and design automation, when a plurality of cores, comprising same sub-chips, are present, the static noise check data for the whole chip is generated from the core-level design data of one of the cores, and the chip-level design data.

The invention discloses a method and a device for measuring energy band bending by photoelectron energy spectrum. The method includes: obtaining the core level photoelectron spectrum of the sample to be tested under N different photoelectron emission angles; N is an integer and N≥4; according to the theoretical relationship between the core level photoelectron spectrum and the corresponding photoelectron emission angle, the photoelectron The theoretical relationship between the emission angle and the corresponding integration depth and the core level photoelectron spectrum under different photoelectron emission angles respectively obtain the energy level values ​​corresponding to N different integration depths; the photoelectron emission angle corresponds to the integration depth one by one; according to the energy The theoretical relationship between the level value and the integration depth, the N integration depths and the energy level values ​​corresponding to each integration depth are fitted to obtain the surface core energy level; the surface core energy level is the corresponding core energy level when the integration depth is 0; according to The theoretical relationship between the energy band bending and the surface core energy level and the value of the surface core energy level can be used to obtain the size of the energy band bending of the sample to be tested. Thereby, the measurement accuracy of band bending can be improved.

This invention discloses a instruction control method for streaming processor, which divides the instruction control into flow-level process and core-level process, the flow-level process is responsible for data scheduling between calculation core and off-chip memory, the core-level process completes data calculation, and the steps is: (1) initializing scalar data of the core-level procedure, (2) preparing vector data for the core-level procedure, (3) start executing the core-level procedure, (4) executing the procedure, (5) storing vector data generated by the procedure into the off-chip memory, (6) reading scalar result of the procedure.

A method for correcting astigmatism of an electronic optical column of an electron emission spectromicroscope, comprising the steps of:forming a reference structure on a surface of a sample comprising a structure of interest to be imaged,imaging the reference structure by the spectromicroscope with secondary electrons and with core level photoelectrons,eliminating astigmatism defects appearing during the imaging of the reference structure with secondary electrons and with core level photoelectrons,a material of the reference structure being chosen such that, during core level photoelectron imaging, the contrast C between the average intensity Ia of the material of the reference structure and the average intensity Ib of the material of the sample is such that:C=Ia-IbIa+Ib≥0.2.