38 results about "Lockstep" patented technology

A data processing apparatus (2) has scalar processing circuitry (32-42) and vector processing circuitry (38, 40, 42). When executing main scalar processing on the scalar processing circuitry (32-42),or main vector processing using a subset of said plurality of lanes on the vector processing circuitry (38, 40, 42), checker processing is executed using at least one lane of the plurality of lanes onthe vector processing circuitry (38, 40, 42), the checker processing comprising operations corresponding to at least part of the main scalar / vector processing. Errors can then be detected based on acomparison of an outcome of the main processing and an outcome of the checker processing. This provides a technique for achieving functional safety in a high end processor with better performance andreduced hardware cost compared to a dual / triple core lockstep approach.

According to at least one embodiment, a method comprises detecting loss of lockstep for a pair of processors. The method further comprises triggering, by firmware, an operating system to idle the processors, and recovering, by the firmware, lockstep between the pair of processors. After lockstep is recovered between the pair of processors, the method further comprises triggering, by the firmware, the operating system to recognize the processors as being available for receiving instructions.

A data processing system and methods for operating the same are disclosed. The method includes detecting a fault by comparing output signals from a first processing core and a second processing core, entering a safe mode based upon detecting the fault, completing transactions while in the safe mode, and determining whether the fault corresponds to a hard error. Based upon the fault corresponding to a hard error, one of processing cores is identified as a faulty core. The faulty core is inhibited from executing instructions and the other processing core is allowed to execute instructions.

In at least one embodiment of the disclosure, a method includes detecting an error in a local memory shared by redundant computing modules executing in delayed lockstep. The method includes pausing execution in the redundant computing modules and handling the error of the local memory. The method includes resuming execution in delayed lockstep of the redundant computing modules in response to the handling of the error.

To facilitate dynamic lockstep support, replacement states and / or logic used to select particular cache lines for replacement with new allocations in accord with replacement algorithms or strategies may be enhanced to provide generally independent replacement contexts for use in respective lockstep and performance modes. In some cases, replacement logic that may be otherwise conventional in its selection of cache lines for new allocations in accord with a first-in, first-out (FIFO), round-robin, random, least recently used (LRU), pseudo LRU, or other replacement algorithm / strategy is at least partially replicated to provide lockstep and performance instances that respectively cover lockstep and performance partitions of a cache. In some cases, a unified instance of replacement logic may be reinitialized with appropriate states at (or coincident with) transitions between performance and lockstep modes of operation.

An integrated circuit (IC) chip includes system circuitry having system memory, and a master processor and a checker processor configured to operate in lockstep; and monitoring circuitry comprising an internal lockstep monitor, a master tracer and a checker tracer. The internal lockstep monitor is configured to: observe states of internal signals of the master processor and the checker processor, compare corresponding observed states of the master processor and the checker processor, and if the corresponding observed states differ: trigger the master tracer to output stored master trace data recorded from the output of the master processor, and trigger the checker tracer to output stored checker trace data recorded from the output of the checker processor.

A processing system comprising a first processing domain and a second processing domain. Each of the first processing domain and the second processing domain comprises a multi-threaded processor core arranged to output a set of internal state signals representative of current states of internal components of the respective processor core. The processing system further comprises a supervisor component arranged to receive the sets of internal state signals output by the processor cores of the first and second processing domains, compare internal state signals output by the processor core of the first processing domain to corresponding internal state signals output by the processor core of the second processing domain, and upon detection of a mismatch between compared internal state signals to initiate a reset of a thread under the execution of which the detected mismatch of internal state signals occurred.

The invention discloses a multi-processor chip error recovery method based on three-mode lockstep. The dual-core lockstep structure based on checkpoint rollback error recovery can quickly check out the wrong CPU through the second slave processor, and can also be performed through subsequent operations. It has a certain ability to detect CPU hard errors, greatly improves the reliability and real-time performance of processor error handling, and at the same time reduces the resource consumption of the three-mode lockstep.

The invention relates to the field of chips, and provides a synchronization method and device for an asynchronous input signal, a central processing unit, and a chip. The method for synchronizing the asynchronous input signal is used in a dual-core lockstep system, the dual-core lockstep system includes a first core and a second core, and the method includes: simultaneously inputting the asynchronous input signal into the first synchronizer and the second synchronizer ; Checking the output signal of the first synchronizer and the output signal of the second synchronizer. The present invention uses two synchronizers for comparative detection, and can capture the failure of any synchronizer according to the comparison verification result information of the output signals of the two synchronizers, thereby ensuring the safety and reliability of the dual-core lockstep system.

Frames from an image stream or streams are processed by independently operating digital signal processors (DSPs), with only frame checking microprocessors operating in a lockstep mode. In one example, two DSP are operating on alternate frames. Each DSP processes the frames and produces prediction values for the next frame. The lockstep microprocessors develop their own next frame prediction. The lockstep processors compare issued frames and previously developed predicted frames for consistency. If the predictions are close enough, the issued frame passes the test. The lockstep processors then compare the issued frame to the preceding two frames for a similar consistency check. If the prior frames are also close enough, the issued frame is acceptable. In another example, hardware checkers are provided to compare the present frame with a larger number of prior frames. The hardware checkers provide comparison results to the lockstep processors to compare against allowable variation limits.

The invention belongs to computer system reliability design technology, and relates to a high-reliability multi-processor computer architecture for real-time monitoring of faults and real-time fault recovery. Including that the processor system adopts a single module design, including a processor unit, a memory unit, a power supply management unit, a clock unit, and a system management unit; the processor unit includes 3 similar or non-similar processor CPUs working in parallel; the The memory unit is composed of 3 random access memory RAMs working in parallel, 2 active and standby read-only memories ROM, and 1 non-volatile memory NVM; the power supply management unit realizes the monitoring and management of the system's dual redundant power supply and Power conversion and management; the clock unit realizes the monitoring and management of dual redundant clock circuits; the system management unit is responsible for monitoring the working conditions of system resources, locating, isolating and recovering resource failures.

In the invention, a problem is solved in which, in order to achieve high performance and high reliability with the conventional multi-core and lockstep core, a redundant lockstep core is necessarily prepared to execute a multi-core program in which an error has occurred, a circuit area increases, and a cost and a power consumption increase. In the invention, a safe operation of a control system is secured by operating a software program operating on a multi-core in which an error has occurred as degenerate software on a core switched from a lockstep operation to a multi-core operation.

The invention relates to a double-core double-lock-step two multiply two structure and a safety platform thereof. The structure comprises a main system and a standby system with the same structure, wherein each of the main system and the standby system adopts a double-core double-lock-step two multiply two structure. The double-core double-lock-step two multiply two structure comprises three processing units, specifically, a first processing unit, a second processing unit and a third processing unit. According to the structure, the double-lock step is realized on the basis of the two double-core processing units, a safe structure which is voted by two multiply two is realized through the third processing unit, the safety platform of the two multiply two structure is realized, and the platform meets the requirements of high safety and high reliability in the safety key field.

The invention provides a high-security computer system based on lock-step and monitoring and a design method thereof. When the processor performs a read operation, the dual processors respectively read data from the same address of the two memories and compare them. If the comparison is correct, the data is sent to the corresponding processor. If the comparison is wrong, the fault handling operation is performed; the comparison module for monitoring and lockstep is set up, and the checkpoint output is added to the load. When the checkpoint arrives, the cross comparison is performed. If the comparison is correct, the system is based on operation; if the comparison is incorrect, the troubleshooting operation is performed. The invention realizes fault detection and location at the instruction level, greatly reduces system faults caused by random faults in the memory, improves the detection rate of the dual-processor common-mode faults of the lockstep module, and further improves the safety of the entire system, effectively It solves the problem that the running speed of dissimilar processors does not match, and reduces the busy waiting time of the monitoring unit.

The invention discloses a low-delay dual-mode lockstep soft error tolerance processor system, which belongs to the technical field of processor error tolerance. The system realizes the detection of soft errors in the processor system through a dual-mode lockstep architecture; by adopting a universal checkpoint and rollback recovery algorithm, the system can cope with a variety of soft errors and improve the reliability of the fault recovery method Universality: The system adopts an adaptive dynamic checkpoint method, predicts the next soft error interval with the soft error interval history table SEIHT and the pattern history table PHT, and increases or decreases the setting frequency of the checkpoint according to the prediction result , this method considers the long-term and short-term characteristics of soft error history at the same time, effectively reduces the average execution time of processor tasks, and solves the problem of large delay time introduced by the current dual-mode lockstep fault-tolerant technology for processors.

The present invention provides a method for modeling and analyzing the reliability of a self-repairing processor to a lockstep system. Firstly, the state of the lockstep system and the self-repairing processor is abstracted into a library set, and the faults of the processor and other components The occurrence and repair actions are abstracted into a transition set, and then the relationship between the place set and the transition set is abstracted into a directed arc set and ignition transition rules between them, and then the failure rate and repair rate information of each component is abstracted into a delay time The average implementation rate of transition elements, thus the GSPN reliability model of the lock-step system is obtained. After the model is initialized, according to the ignition transition rules, all the states reachable by the lockstep system are obtained, and then the isomorphic Markov chain of the GSPN reliability model is constructed, and the cumulative probability function equation of the reachable states of the GSPN reliability model is obtained and solved , to obtain the reliability function of the lock-step system, so as to complete the reliability analysis of the lock-step system. The modeling process of the invention is simple, and the reliability function of the system can be obtained accurately.

Aspects disclosed herein relate to periodic non-invasive diagnostics of lockstep systems. An exemplary method includes comparing execution of a program on a first processing system of a plurality of processing systems to execution of the program on a second processing system of the plurality of processing systems using a first comparator circuit , comparing said execution of said program on said first processing system to said execution of said program on said second processing system using a second comparator circuit, and using said first comparison A diagnostic routine is run on the second comparator circuit while the comparison by the second comparator circuit is in progress.

A method of tying related process threads within non-related applications together in terms of memory paging behavior. In a data processing system, a first process thread is related to one or more “partner” threads within separate high latency storage locations. The kernel analyzes the memory “page-in” patterns of multiple threads and identifies one or more partner threads of the first thread based on user input, observed memory page-in patterns, and / or pre-defined identification information within the thread data structures. The kernel marks the first thread and its corresponding related partner threads with a unique thread identifier. When the first thread is subsequently paged into a lower latency memory, the kernel also pages-in the related partner threads that are marked with the unique thread identifier in lockstep. Tying related threads from non-related applications together in terms of memory paging behavior thus eliminates memory management delays.