75 results about "Hard error" patented technology

A disk drive utilizes a unique write condition for each of the transducers within the drive. Each write condition is determined based upon the specific properties of the corresponding transducer. The write condition information is preferably stored within a memory within the disk drive. When a write operation is performed, the appropriate write condition for the corresponding transducer is used to determine when to write data to the disk. A write condition will typically include one or more individual write criteria. For example, a write condition can specify a write threshold value to be used during a write operation. A write fault threshold value is selected for each transducer by determining a position error distribution corresponding to that transducer wherein the position error distribution is essentially a function of random noise associated with the disk drive, and by using that distribution to determine allowable off-track threshold value (WFL), will protect the drive from encroachments.

A data processing apparatus and method are provided for handling hard errors occurring in a cache of the data processing apparatus. The cache storage comprising data storage having a plurality of cache lines for storing data values, and address storage having a plurality of entries, with each entry identifying for an associated cache line an address indication value, and each entry having associated error data. In response to an access request, a lookup procedure is performed to determine with reference to the address indication value held in at least one entry of the address storage whether a hit condition exists in one of the cache lines. Further, error detection circuitry determines with reference to the error data associated with the at least one entry of the address storage whether an error condition exists for that entry. Additionally, cache location avoid storage is provided having at least one record, with each record being used to store a cache line identifier identifying a specific cache line. On detection of the error condition, one of the records in the cache location avoid storage is allocated to store the cache line identifier for the specific cache line associated with the entry for which the error condition was detected. Further, the error detection circuitry causes a clean and invalidate operation to be performed in respect of the specific cache line, and the access request is then re-performed. The cache access circuitry is arranged to exclude any specific cache line identified in the cache location avoid storage from the lookup procedure. This mechanism provides a very simple and effective mechanism for handling hard errors that manifest themselves within a cache during use, so as to ensure correct operation of the cache in the presence of such hard errors. Further, the technique can be employed not only in association with write through caches but also write back caches, thus providing a very flexible solution.

Hard errors in the memory array can be detected and corrected in real-time using reusable entries in an error status buffer. Data may be rewritten to a portion of a memory array and a register in response to a first error in data read from the portion of the memory array. The rewritten data may then be written from the register to an entry of an error status buffer in response to the rewritten data read from the register differing from the rewritten data read from the portion of the memory array.

In one embodiment, a memory controller comprises a check bit encoder circuit coupled to receive a data block to be written to memory, a check / correct circuit coupled to receive an encoded data block read from the memory, and a hard failure detection circuit coupled to the check / correct circuit. The check bit encoder circuit is configured to generate a corresponding encoded data block comprising the data block, a first plurality of check bits, and a second plurality of check bits. The check / correct circuit is configured to detect an error in the encoded data block responsive to the first check bits, the second check bits, and the data block within the encoded data block, which is logically arranged as an array of R rows and N columns, wherein R and N are positive integers. Each of the first check bits covers a respective row of the array, and the check / correct circuit is configured to generate a first syndrome corresponding to the first plurality of check bits. A presence of more than one binary one in the first syndrome indicates a multi-bit error. Responsive to detecting the multi-bit error, the hard failure detection circuit is configured to perform a plurality of memory read / write operations to the memory locations in which the encoded data block is stored to identify a hard error failure in the memory.

A method and system for error recovery of a hardware device is provided. The method includes detecting a target hard error indication from the hardware device by comparing the hard error indication to signatures of hard error indications which indicate a temporary failing and modifying the reported error to a stalling indication. The hardware device is allowed to recover in a predefined time period or by issuing one or more resets, or both. A hard error indication usually instigates an external error recovery of the hardware device and the method temporarily stalls such external error recovery.