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Identification and mitigation of hard errors in memory systems

A technology of memory and storage unit, applied in the field of hard errors, which can solve the problems of soft decoding algorithm performance and hard error rate deterioration

Inactive Publication Date: 2012-12-12
MARVELL WORLD TRADE LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The performance of soft decoding algorithms degrades significantly even when the hard error rate in the data is relatively low

Method used

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  • Identification and mitigation of hard errors in memory systems
  • Identification and mitigation of hard errors in memory systems
  • Identification and mitigation of hard errors in memory systems

Examples

Experimental program
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Embodiment Construction

[0021] figure 1 An example of memory system 10 is schematically illustrated. Memory system 10 includes memory 14 . Memory 14 is any suitable type of memory, for example, volatile memory (eg, random access memory of a suitable type), non-volatile memory (eg, read-only memory), or the like. In an embodiment, memory 14 is an electrically erasable programmable read-only memory (EEPROM), such as flash memory.

[0022] Although in figure 1 Not shown, the memory 14 includes a plurality of storage blocks, wherein each storage block includes a plurality of storage units, and each storage unit stores one or more bits of data. For example, each memory cell of memory 14 may be a single-level cell (SLC), which stores a single bit of data. In another example, each memory cell of memory 14 may be a multi-level cell (MLC), which stores multiple bits of data.

[0023] The memory system 10 includes a read control module 20 that includes a read module 24 , an LLR estimation module 28 , a ...

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Abstract

The invention relates to dentification and mitigation of hard errors in memory systems. Embodiments provide a method comprising estimating a first set of log-likelihood ratio (LLR) values for a plurality of memory cells of a memory; based on the first set of LLR values, performing a first error correcting code (ECC) decoding operation; in response to determining a failure of the first ECC decoding operation, generating, by adjusting the first set of LLR values, a second set of LLR values for the plurality of memory cells; and based on the second set of LLR values, performing a second ECC decoding operation.

Description

[0001] Cross References to Related Applications [0002] This disclosure claims priority to U.S. Provisional Patent Application No. 61 / 494,333, filed June 7, 2011, and U.S. Provisional Patent Application No. 61 / 497,907, filed June 16, 2011, the entire disclosures of which are hereby incorporated by reference contains its entire contents. technical field [0003] Embodiments of the present disclosure relate to the field of memory systems, and more particularly to hard errors in memory systems. Background technique [0004] The background description provided herein is for the purpose of generally presenting the context of the disclosure. The work of the presently named inventors described in this background section, as well as aspects of this specification that are not otherwise adjudged to be prior art at the filing date, are not intended to be expressly or implicitly admitted to be prior art with respect to the present disclosure. [0005] Memory systems (eg, flash memo...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/42
CPCG11C29/52G06F11/1048G11C2029/0411G11C29/028G06F11/1072H03M13/45
Inventor S·K·奇拉帕加里G·伯德陈振钢
Owner MARVELL WORLD TRADE LTD
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