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Error detection using vector processing circuitry

A technique for processing circuits, error detection, applied to error detection. domain, able to address issues such as performance processor circuit area and power consumption overhead impact

Active Publication Date: 2019-08-30
ARM LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, providing such an error detection mechanism may have an impact on the performance achieved by the conventional processing performed by the processor, as well as on the circuit area and power consumption overhead of the processor

Method used

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  • Error detection using vector processing circuitry
  • Error detection using vector processing circuitry
  • Error detection using vector processing circuitry

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Embodiment Construction

[0030] The emergence of smart and potentially semi-autonomous vehicles (cars, drones, etc.) represents a growing market for high-performance processors. However, safety-critical systems require components to be authenticated to meet a specific integrity level. For example, the Automotive Safety Integrity Level (ASIL) risk classification scheme offers several levels of classification that vary according to the percentage of failures that can be detected. Processors that focus on functional safety can be designed to include error detection mechanisms (eg, in-circuit logic built-in self-test, dedicated hardware checkers, etc.), which can enable them to be classified at the highest classification level (ASIL D). However, application processors are more concerned with performance in a general-purpose environment, and are unlikely to support this level of increased complexity, since the cost and effort of including error detection mechanisms would be infeasible for more complex high...

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Abstract

A data processing apparatus (2) has scalar processing circuitry (32-42) and vector processing circuitry (38, 40, 42). When executing main scalar processing on the scalar processing circuitry (32-42),or main vector processing using a subset of said plurality of lanes on the vector processing circuitry (38, 40, 42), checker processing is executed using at least one lane of the plurality of lanes onthe vector processing circuitry (38, 40, 42), the checker processing comprising operations corresponding to at least part of the main scalar / vector processing. Errors can then be detected based on acomparison of an outcome of the main processing and an outcome of the checker processing. This provides a technique for achieving functional safety in a high end processor with better performance andreduced hardware cost compared to a dual / triple core lockstep approach.

Description

technical field [0001] The technology relates to the field of data processing. More specifically, it relates to error detection. Background technique [0002] Data processing apparatus may be affected by random hardware failures (eg permanent failures caused by shorts or opens in integrated circuits, or temporary failures such as bit flips caused by exposure to natural radiation or particle impact). For certain areas of use, for example in the automotive sector where safety may be critical, to ensure functional safety the processor can be provided with error detection mechanisms for detecting errors and ensuring safe operation in the presence of such errors operate. However, providing such an error detection mechanism may have an impact on the performance achieved by conventional processing performed by the processor, as well as on the processor's circuit area and power consumption overhead. Contents of the invention [0003] At least one example provides an error detec...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/16
CPCG06F11/1637G06F11/1679G06F11/1683G06F2201/845G06F8/41G06F9/3836G06F9/3889G06F9/30145G06F9/30038G06F9/30036G06F11/1641G06F9/3017G06F9/30043G06F11/0721G06F11/0751
Inventor 马蒂亚斯·洛塔尔·伯特歇尔姆布·埃约勒纳撒尼尔·普瑞米利尤
Owner ARM LTD
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