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Image compression multi-core synchronous fault-tolerance method, computer and processor

An image compression and image processing technology, applied in the direction of processor architecture/configuration, computing, electrical digital data processing, etc., can solve the problems of performance waste, inflexible and inflexible binding mechanism between main core and redundant core, etc.

Inactive Publication Date: 2018-05-15
NAT UNIV OF DEFENSE TECH
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  • Abstract
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  • Claims
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AI Technical Summary

Problems solved by technology

In particular, the core-level redundancy fault tolerance currently has the following problems: (1) idleness in the redundancy causes performance waste: the core that completes the computing task first between the main core and the redundant core needs to wait for the other core to complete; (2) There is a waste of performance during the result verification: when the main core performs the result verification operation, the redundant core needs to be idle and wait for the result verification operation to complete, resulting in a waste of performance; (3) The binding mechanism between the main core and the redundant core is not flexible : Whether it is static binding or dynamic binding, the main core and redundant core work in pairs, which is not flexible enough, inconvenient to expand, and cannot adapt to the working state of an odd number of cores
[0003] To sum up, the problems existing in the existing technology are: the current nuclear-level redundancy fault tolerance has idleness in the redundancy, which causes performance waste; there is performance waste in the result verification; the binding mechanism between the main core and the redundant core is not flexible
The main reason for the problem is that the previously adopted multi-core parallel mechanism cannot fully meet the needs of fault tolerance. It is necessary to select an appropriate multi-merge parallel mechanism and design a multi-core parallel system that meets the needs of fault tolerance.

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  • Image compression multi-core synchronous fault-tolerance method, computer and processor
  • Image compression multi-core synchronous fault-tolerance method, computer and processor
  • Image compression multi-core synchronous fault-tolerance method, computer and processor

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Embodiment Construction

[0042] In order to make the object, technical solution and advantages of the present invention more clear, the present invention will be further described in detail below in conjunction with the examples. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0043] The history of computer development shows that many methods that were originally implemented in hardware can also be implemented in software. On COTS microprocessors, the lack of fault tolerance of COTS devices can be made up for by implementing software fault-tolerant technology for hardware transient faults. Many experiments have been carried out at home and abroad to explore the application of COTS processors in the space environment. The results show that the software fault-tolerant method for hardware faults can effectively improve the reliability of space computers based on COTS devices, and can well cope with t...

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Abstract

The invention belongs to the technical field of hardware transient fault detection and recovery, and discloses an image compression multi-core synchronous fault-tolerance method, a computer and a processor. The method comprises the steps of constructing a synchronous image compression module, and making a single-core image processing program to conduct transplantation and optimization on a multi-core processor; according to existing core-level redundancy fault-tolerance characteristics, determining an unbounded asynchronous redundancy fault-tolerance model; according to the unbounded asynchronous redundancy fault-tolerance model, combining the synchronous image compression module to add a redundancy fault-tolerance function to an image compression system. According to the image compressionmulti-core synchronous fault-tolerance method, by achieving multi-core synchronous work on a main-core design management layer, the processor can be flexibly and conveniently transplanted on different kinds of hardware; the situations that there is a core being vacant to wait for data transmission and comparison is completed during synchronous redundancy fault tolerance are avoided; result comparison is conducted after two times of calculation; the extra expenditure caused by the data transmission is avoided, and memory access pressure of the system can also be reduced because the two operations are not overlapped in terms of time.

Description

technical field [0001] The invention belongs to the technical field of hardware transient fault detection and repair, and in particular relates to an image compression multi-core parallel fault-tolerant method, a computer and a processor. Background technique [0002] Space exploration activities require a lot of investment and high risk, and have extremely high requirements for computing reliability. The main factor affecting the safety of space probes in space is the radiation of cosmic rays, because there are a large number of high-energy particles including electrons, protons, particles and heavy ions in the cosmic environment. When the cosmic rays composed of these particles bombard the semiconductor of the aerospace computer When the circuit is damaged, it may cause a transient change in the stored power in the PN structure. This transient fault is also commonly referred to as the single event effect SEE (Single Event Effect). Although single event effects generally d...

Claims

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Application Information

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IPC IPC(8): G06F11/07G06T1/20
CPCG06F11/0724G06F11/0793G06T1/20
Inventor 谭庆平唐国斐李盼盼徐建军邵则铭曾平张南孟宪凯张浩宇邓锦洲谢勤政颜颖刘鑫昊
Owner NAT UNIV OF DEFENSE TECH
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