717 results about "Clock synchronisation" patented technology

In a multiprocessor system that includes a plurality of processor modules, each one of which includes its own internal clock, one of the plurality of processor modules is designated as a master processor module having a master internal clock. Each other processor module is designated as a slave processor module having a slave processor module internal clock. Each slave processor module synchronizes its internal clock with the master internal clock.

The invention provides a clock synchronization method among wireless network devices. The method comprises the steps that 1, a clock source device and at least one clock slave device are in network interconnection; 2, the clock source device obtains a reference clock, and the clock slave devices obtain unsynchronized reference clocks; 3, the clock source device interacts clock information with the clock slave devices through clock synchronization frames; 4, the clock source device transmits information containing the frequency and phase of the reference clock to the clock slave devices; the CPU processors in the clock slave devices calculate the reference clock of the clock source device and calibrate own reference clocks according to the reference clock; and the clock synchronization among the wireless network devices is realized through the steps. The synchronized reference clock can be used for synchronous scheduling of CPU system tasks, synchronous control of performance of instructions, high-precision synchronous measurement of external signals and synchronous measurement of high-speed moving objects, basic wireless take scheduling can be satisfied, and the synchronous awakening tasks of the devices in an ultra low-power-consumption application can be satisfied.

A method of synchronising the operation of a plurality of SuperSpeed USB devices and a plurality of non-SuperSpeed USB devices is provided. The method includes establishing a SuperSpeed synchronisation channel for each of the plurality of SuperSpeed USB devices; establishing a non-SuperSpeed synchronisation channel for each of the plurality of non-SuperSpeed USB devices; synchronising a respective local clock of each of the plurality of SuperSpeed USB devices; synchronising a respective local clock of each of the plurality of non-SuperSpeed USB devices; and synchronising the SuperSpeed and non-SuperSpeed synchronisation channels so that the SuperSpeed and non-SuperSpeed devices can operate in synchrony.

A clock synchroniser, and clock and data recovery apparatus incorporating the clock synchroniser, are described, together with corresponding clock synchronisation methods. The clock synchroniser incorporates an elastic buffer. A received clock signal RCK is used to clock data into the buffer, and a locally generated clock LCK is used to clock data out of the buffer. The local clock is synthesised using a PLL, and a fill-level signal from the elastic buffer is used to control to local clock frequency to maintain a desired average quantity of data in the buffer, thereby achieving synchronisation of the received and local clocks. In preferred embodiments the fill-level signal is used to control a variable divider in the feedback path of the PLL, which is supplied with a highly stable reference signal. A synchronised, and low-jitter local clock is thus produced. Preferably, the elastic buffer employs counters of relatively wide word width, and a storage array of much reduced depth, read and write pointers being provided by just a few of the least significant bits of the words.

A method for synchronising a clock signal in a basestation of a wireless telecommunications system is described. The basestation has a reference clock signal and is operable to communicate with wireless mobile terminals and with a packet switched network. The method comprises detecting a radio frequency clock synchronisation signal from a wireless telecommunications network, and synchronising the reference clock signal of the basestation in dependence upon the detected radio frequency clock synchronisation signal.

A clock synchronization buffer for a counter clock flow pipelined circuit including a cascade of processing modules that receive data from a previous module and provide output results to a following module. The clock synchronization buffer receives a clock input signal and provides clock signals to a local processing module and to the next pipeline stage. The clock synchronization buffer includes a selectable delay stage that receives a clock input signal and a delay select signal and outputs a clock signal having a selected delay. An amplifier connected to the selectable delay stage provides the delayed clock signal to a local processing module that corresponds to the clock synchronization buffer circuit. An inverting amplifier connected to the selectable delay stage provides the delayed clock signal to the next pipeline stage. A clock synchronization controller synchronizes the phases of reference clock input and synchronized clock input signals.

The invention discloses an intelligent transformer station process layer information acquisition, conversion and transmission device and a control method thereof. The intelligent transformer station process layer data acquisition, conversion and transmission device comprises a process layer sampled value conversion and merging subsystem and an FPGA (Field Programmable Gate Array) subsystem, wherein the process layer sampled value conversion and merging subsystem comprises a multi-channel AD (Analog-to-digital Conversion) and conditioning circuit module, a clock synchronization module, a high-speed CPLD (Complex Programmable Logic Device) module, a DSP (Digital Signal Processor) module and other protocol processing modules; the FPGA subsystem comprises GOOSE (Generic Object Oriented Substation Event) message identification module, and an IEC (International Electrotechnical Commission) 61850-9-2 protocol processing model module; the DSP module is connected with the CPLD module and the clock synchronization module through a parallel bus; the CPLD module is connected with the multi-channel AD and conditioning circuit module through a parallel data channel; pulse signals are collected by the clock synchronization module through a parallel port; and the FPGA subsystem is connected with the process layer sampled value conversion and merging subsystem through an FIFO (First-in, First-out) interface. The intelligent transformer station process layer information acquisition, conversion and transmission device integrates sampling, protocol conversion and data merging, the intermediate process for data transmission is reduced, and real-time transmission of data is facilitated.