43results about How to "Simply fabricated" patented technology

The invention relates to a process by which a multi-image type hologram wherein one 3D image changes over to another depending on a viewing direction can be fabricated in simple construction and a multi-image type hologram fabricated by that process. According to the process for the fabrication of a multi-image type hologram wherein one image changes over to another depending on a viewing direction, the area of a hologram recording material is divided into a plurality of sub-areas 11₁, 11₂ and 11₃. Objects to be displayed on different images are holo-graphically recorded in the respective sub-areas, using reference light having the same angle of incidence, thereby recording the first-stage hologram 11. Object images O₁′, O2′ and O₃′ recorded in the respective sub-areas 11₁, 11₂ and 11₃ are simultaneously reconstructed from the recorded first-stage hologram 11, so that a second-stage hologram recording material 21 is located near the reconstructed object images O₁′, O₂′ and O₃′ for recording them as a reflection or transmission type volume hologram.

A display driver backplane, a display device and a fabrication method thereof are disclosed. The display driver backplane includes: a first semiconductor laminate including pixel driver array consisting of a plurality of pixel driver elements and first peripheral circuit unit; first electrode array formed on second surface of first semiconductor laminate; a second semiconductor laminate containing a second peripheral circuit unit, wherein a first surface of the second semiconductor laminate is bonded to a first surface of first semiconductor laminate; and first vias that are formed within first semiconductor laminate and electrically interconnect first-electrode array and pixel-driver array. The present invention addresses prior-art issues of high difficulty in fabricating transistors with different capabilities in the same layer and costly interconnection between transistors in different chips by employing a technique in which two or three chips are stacked together, and hence achieves significant improvements in device performance and reductions in cost.

A digital garment and a fabrication method thereof are provided. The digital garment is fabricated using a knitting technique. The digital garment comprises a plurality of knitting yarns forming loops at regular intervals and interwoven through the loops, and one or more conductive digital yarns tied to the loops of the knitting yarns to form high-speed information communication circuits. The knitting yarns and the digital yarns are knitted together into a garment. During knitting, the digital yarns are used to form high-speed information communication circuits in a rapid and economical manner.

Provided is a stack package comprising: a substrate comprising a cavity; a first semiconductor chip disposed in the cavity; and a second semiconductor chip stacked on the substrate and electrically connected to the substrate by a plurality of conductive external terminals such as conductive bumps. Since both a horizontal packaging method using bonding wires and a flip-chip packaging method are used and the bonding wires of the horizontal package and the conductive external terminals for the flip-chip bonding are formed on substantially the same plane, the total height of the stack package is reduced.

The present invention provides a thin-film transistor (TFT) substrate, which can be fabricated simply and at reduced cost, and a method of fabricating the TFT substrate. The TFT substrate includes: an insulating substrate; gate wiring that extends on the insulating substrate in a first direction; data wiring that extends on the gate wiring in a second direction, and includes a lower layer and an upper layer; and a semiconductor pattern that is disposed under the data wiring and has substantially the same shape as the data wiring except for a channel region, wherein root-mean-square roughness of a top surface of the data wiring is 3 nm or less.

The semiconductor device includes: a first MIS transistor formed on a first region of a first conductivity type in a semiconductor substrate; and a second MIS transistor formed on a second region of a second conductivity type in the semiconductor substrate. The first MIS transistor has a first gate insulating film and a first gate electrode formed on the first region, first sidewalls formed on the side faces of the first gate electrode, and first source/drain regions made of silicon formed in portions of the first region. The second MIS transistor has a second gate insulating film and a second gate electrode formed on the second region, second sidewalls formed on the side faces of the second gate electrode, and second source/drain regions including silicon germanium formed in portions of the second region. The second sidewalls are smaller in height than the first sidewalls.

An adhesive as a heat resistant rubber-based adhesive is applied to a region (peripheral region) of integration of a metal sheet (Al sheet) and a resin and to a region (peripheral region) of integration of a fiber sheet (CF sheet) and a resin. The metal sheet and fiber sheet are temporarily fixed to dry the adhesive, then, the joined article is accommodated in an injection molding machine, a polycarbonate resin is injected, and the joined article (metal sheet and fiber sheet) is integrally molded with the polycarbonate resin.

Disclosed are a chip scale package and a method of fabricating the chip scale package. The chip scale package comprises conductive layers with a designated depth formed on an upper and a lower surfaces of a chip, and electrode surfaces formed on the same side surfaces of the conductive layers, which are connected to corresponding connection pads of a printed circuit board. The chip scale package is miniaturized in the whole package size. Further, the method of fabricating the chip scale package does not require a wire-bonding step or a via hole forming step, thereby simplifying the fabrication process of the chip scale package and improving the reliability of the chip scale package.

An apparatus for measuring transmissivity of a patterned glass substrate. A beam radiator radiates a laser beam. A collimation lens collimates the laser beam radiated from the laser beam radiator. A beam expander expands a size of the laser beam collimated by the collimation lens. A detector has a light-receiving section, which receives the laser beam that has passed through the patterned glass substrate after having been expanded by the beam expander. A measuring section measures a transmissivity of the patterned glass substrate using the laser beam received by the detector.