53results about How to "Reduced Junction Leakage Current" patented technology

A method for manufacturing a MOS transistors in a semiconductor device includes the step of implanting a dopant in a channel layer or source / drain regions by using a multi-step implantation and an associated multi-step heat treatment, wherein the multi-step implantation includes a number of steps of implantation each for implanting the dopant at a dosage lower than 1x1013 / cm2. The total dosage of the multi-step implantation ranges between 1x1013 / cm2 and 3x1013 / cm2.

A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which suppresses a floating-body effect and improves isolation performance and breakdown voltage, and a method of manufacturing the semiconductor device can be obtained.

The invention provides a transistor and a manufacturing method for the same. The method includes the steps: providing a semiconductor substrate with a formed active layer; forming buried layers spaced from the active layer on the surface of the semiconductor substrate on two sides of the active layer; forming first epitaxial layers flush with the active layer on the surfaces of the buried layers and in the space between each buried layer and the active layer; forming grooves exposed out of the semiconductor substrate in the first epitaxial layers, wherein the grooves are positioned among the buried layers and the active layer; forming buried side walls in the grooves, wherein the thickness of each buried side wall is smaller than the depth of each groove; forming second epitaxial layers on the surfaces of the buried side walls, the active layer and the first epitaxial layers; forming gate structures on the surfaces of the second epitaxial layers above the active layer; and forming a source region and a drain region in the second epitaxial layer and the first epitaxial layer on two sides of each gate structure, wherein the source region and the drain region are positioned on two sides of an isolating side wall. By the aid of the method, the short-channel effect and the performance of the transistor are improved.

Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.

The method of manufacturing a semiconductor device comprises forming a metal film over silicon regions and insulating films; performing a first heat treatment under an oxygen atmosphere containing oxygen as a main ingredient, to form a first silicide film in the silicon region by reacting the metal film and the silicon region, and to simultaneously form a metal oxide by oxidizing the entire surface of the metal film from the surface side thereof; and selectively removing the metal oxide and the unreacted metal film using a chemical.

The invention relates to a semiconductor structure and a manufacturing method thereof. The method comprises the steps of providing a base, wherein the base comprises a first depth region, a second depth region and a third depth region; forming a buffer doping ion region in the base of the second depth region; removing a part of the base of the second depth region and the third depth region to form a substrate and fin parts protruding out of the substrate; forming an isolation structures with thickness equal to the depth of the second depth region on the substrate, wherein the fin part exposed out of the isolation structure is a fin part first region, and a part which is not exposed is a fin part second region; forming a punchthrough-prevention doping ion region with an ion type same as that of the buffer doping ion region in the fin part second region, wherein the ion concentration of the punchthrough-prevention doping ion region is larger than that of the buffer doping ion region; forming a grid structure bridging the fin parts; and forming a source-drain doping region in the fin part first region at two sides of the grid structure. The ion concentration of the punchthrough-prevention doping ion region is between that of the source-drain doping region and that of the buffer doping ion region, and thus, the junction leak current between the source-drain doping region and the substrate is reduced.