Semiconductor structure, preparation method of transistor structure and semiconductor processing device

Abstract

The invention discloses a semiconductor structure based on low-temperature ion implantation, transistor preparation and a semiconductor processing device. The method comprises the steps of: providinga to-be-processed structure, and defining an ion implantation layer region with an ion implantation surface; cooling the to-be-processed structure, performing ion implantation from the ion implantation surface, wherein in the ion implantation process, an ion implantation layer area is converted into a recovery damage crystallization layer area and a lattice damage amorphous layer area, the self-annealing effect in the ion implantation layer area is relieved through cooling treatment, and the size of the recovery damage crystallization layer area is reduced; and performing annealing treatment,converting the lattice damage amorphous layer area into a recrystallization layer area, and converting the recovery damage crystallization layer area into a crystallization defect layer area. The to-be-processed structure is cooled in the ion implantation process, ion implantation is carried out under the low-temperature condition, and the self-annealing effect in the ion implantation process is relieved, so that the EOR defect after annealing is reduced, the junction leakage current is reduced, and the power consumption of an electronic device is reduced.

Description

technical field [0001] The invention belongs to the technical field of semiconductor device structure preparation, and in particular relates to a method for preparing a semiconductor structure based on low-temperature ion implantation, a method for preparing a transistor structure, and semiconductor processing equipment. Background technique [0002] Dynamic Random Access Memory (DRAM for short) is a semiconductor storage device commonly used in computers, and is composed of many repeated storage units. Each memory cell usually includes a capacitor and a transistor; the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor; the voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line Read the data information stored in the capacitor, or write the data information into the capacitor through the bit line for storage. At present, in th...

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Problems solved by technology

The EOR (End of Range) defect formed after ion implantation and annealing in semiconductor manufacturing will lead to junction leakage (Junction leakage). In the prior art, such as in the preparation of source and drain regions, the EOR defect layer is relatively thick, resulting Leakage current (10 -5 ~10 -8 A / CM 2 ), thus increasing the power consumption of electronic devices

[0004] Therefore, how to provide a method for preparing a semiconductor structure, a transistor structure, and a semiconductor device is necessary to solve the problem that EOR defects have a serious impact on device performance in the prior art

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