Semiconductor structure forming method

Abstract

The invention discloses a semiconductor structure forming method. The method comprises steps: a substrate is provided, wherein the substrate comprises a first area and a second area, surfaces of the first area and the second area of the substrate are provided with pseudo gate structures respectively, and the pseudo gate structure comprises a pseudo gate layer and an initial mask layer located on the surface of the pseudo gate layer; a first stress layer is formed in the substrate at two sides of the pseudo gate structure in the first area; a first deep injection process is adopted to dope ions of a first type in the first stress layer and in the partial substrate at the bottom part of the first stress layer; after the first deep injection process, the thickness of the initial mask layer is thinned, and a first mask layer is formed; a second source-drain area is formed in the substrate at two sides of the pseudo gate structure in the second area; and after the first mask layer and the second source-drain area are formed, a dielectric layer is formed on the surface of the substrate, the dielectric layer covers the side wall surface of the pseudo gate structure, and the surface of the dielectric layer is flush with the top surface of the first mask layer. The performance of the formed semiconductor structure is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in integrated circuits, especially MOS (Metal Oxide Semiconductor, metal-oxide-semiconductor) devices, is continuously reduced to meet the miniaturization and development of integrated circuits. Integration requirements, and transistor devices are one of the important components of MOS devices. [0003] For transistor devices, as the size of the transistor continues to shrink, the gate dielectric layer formed of silicon oxide or silicon oxynitride material in the prior art cannot meet the performance requirements of the transistor. In particular, transistors formed with silicon oxide or silicon oxynitride as the gate dielectric layer are prone to a series of problems such as ...

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Problems solved by technology

[0005] However, as the size of semiconductor devices shrinks, the size of the high-K metal-gate transistor is also reduced accordingly, which increases the difficulty of manufacturing the high-K metal-gate transistor, resulting in a decrease in the performance of the high-K metal-gate transistor

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