38results about How to "Reduce emission efficiency" patented technology

The invention relates to a vacuum aluminizing method of the surface of a neodymium-iron-boron permanent magnet. The method sequentially comprises the following steps of: (1) polishing and cleaning the surface of the neodymium-iron-boron permanent magnet by adopting a wet method; (2) putting the neodymium-iron-boron permanent magnet on a rotating workpiece fame in a film plating chamber to ensure that the temperature of the neodymium-iron-boron permanent magnet is kept between 250 DEG C and 300 DEG C; (3) starting a vacuum pump on the film plating chamber and adjusting the vacuum degree of thefilm plating chamber to be 1-9*10<-3>Pa; (4) meanwhile, starting multi-arc cathode evaporators at both sides of the film plating chamber, a plane magnetic sputtering target and the rotating workpieceframe to carry out magnetic control multi-arc sputtering for 2-7 hours; (5) maintaining the film plating chamber to be cooled for 30-60 minutes under vacuum, aerating, opening the chamber, taking outthe aluminized neodymium-iron-boron permanent magnet and carrying out passivation with a non-chrome passivation solution. High energy ions generated by magnetron sputtering strike low-energy ions generated by the multi-arc method so as to promote the low-energy ions to generate more ionization, wherein the speeds and the trends of the high-energy ions and the low-energy ions are uniform, thus theefficiency is improved.

The invention provides an IGBT device and a manufacturing method thereof. The IGBT device includes: a substrate, the substrate includes opposite first main surfaces and second main surfaces, the first main surface is formed with a front structure of the IGBT device, and the IGBT device includes The active region, the transition region and the terminal region; the oxygen ion defect layer, formed in the second main surface of the transition region and the terminal region; the collector region, formed on the second main surface of the substrate; the hydrogen ion doped region, formed In the second main surface of the substrate, the oxygen ion defect layer is located in the hydrogen ion doped region, wherein the oxygen ions in the oxygen ion defect layer serve as adsorbents for hydrogen ions so as to increase the doping of hydrogen ions in the hydrogen ion doped region. impurity concentration. The present invention reduces the emission efficiency of the transition region and the terminal region when the IGBT device is turned on, and at the same time increases the recombination speed of electrons and holes in the transition region and the terminal region when the IGBT device is turned off, thereby effectively alleviating the current concentration problem existing in the transition region , Improve the reliability of the IGBT chip.

The invention provides a transverse insulated gate bipolar transistor with high thermal carrier reliability, which comprises a P-type substrate with a buried oxide layer. An N-type epitaxial layer is provided on the buried oxide layer. In the N-type epitaxial layer, an N-type buffer well and a P-type body region are provided. In the N-type buffer well, a P-type positive region is provided. In the P-type body region, an N-type negative region and a P-type body contact region are provided. The surface of the N-type epitaxial layer is provided with a gate oxide layer and a field oxide layer. A polysilicon gate is provided on the surface of the gate oxide layer, and polysilicon is arranged on the right upper surface of the field oxide layer. The P-type positive region consists of block shaped N-type regions arranged in rows; in the N-type buffer region, a floating hollow N-type contact region is provided. The P-type positive region is arranged in the floating hollow N-type contact region, and each of the block shaped N-type regions is surrounded by the floating hollow N-type contact region on three sides. And the other end of the field oxide layer extends toward the P-type positive region and ends at the floating hollow N-type contact region. According to the invention, it is possible to reduce the emission efficiency of a parasitic PNP transistor, reduce the hot carrier damage in the on-state and the switching state, and improve the reliability of devices.

The present application relates to the field of carrier communication, and in particular, to a power line carrier communication device and method. The device includes: a communication processing unit for modulating a communication signal into a control signal, the communication signal including communication data; a switch network unit for outputting a multi-level carrier signal corresponding to the communication signal according to the control signal, wherein the carrier contained in the signal n The harmonic components of the +1 order and the following orders are respectively less than or equal to the first threshold value, n represents the number of levels contained in the carrier signal, and n is an odd number greater than or equal to 3; the impedance network unit is used to filter the carrier signal and couple it to the power line. The invention improves the transmission efficiency of the power line carrier signal, greatly reduces the transmission power of the power line carrier signal; realizes that in the conversion process of the carrier signal, all or part of the low-order harmonics of the n+1 order and below are eliminated, reducing the reduction of the power line carrier signal. The requirement of the output low-pass filter greatly reduces the size and cost of the filter.

The invention belongs to the field of power semiconductor device testing, and in particular relates to a semiconductor device with a buffer layer structure, which includes a first dopant region, a second dopant region, and a third dopant region arranged in sequence, and also includes an alternative or a plurality of upper dopant regions, lower dopant regions, and middle dopant regions arranged in combination; the upper dopant region is located between the first dopant region and the second dopant region; the The lower dopant region is located between the second dopant region and the third dopant region; the middle dopant region is located in the middle of the second dopant region. The advantage of the present invention is that a smaller drain can be achieved. Current, thereby improving the withstand voltage capability of the device, as well as the highest junction temperature that can be operated, and increasing the flow capacity of the device.