829results about How to "Reduce conduction" patented technology

A semiconductor device including a transistor and a connection portion is provided. The transistor includes a gate electrode, a first insulating film over the gate electrode, an oxide semiconductor film over the first insulating film and at a position overlapping with the gate electrode, and source and drain electrodes electrically connected to the oxide semiconductor film; and the connection portion includes a first wiring on the same surface as a surface on which the gate electrode is formed, a second wiring on the same surface as a surface on which the source and drain electrodes are formed, and a third wiring connecting the first wiring and the second wiring. The distance between an upper end portion and a lower end portion of the second wiring is longer than the distance between an upper end portion and a lower end portion of each of the source and drain electrodes.

The present application discloses a semiconductor device formed on a SOI substrate which comprises a buried insulating layer and a semiconductor layer on the buried insulating layer and a method for manufacturing the same, wherein a fin of semiconductive material having two opposing sides perpendicular to a main surface of the SOI substrate is provided in the semiconductor layer, said semiconductor device comprising: a source region and a drain region provided at two ends of the fin respectively; a channel region provided at a central portion of the fin; and a stack of gate dielectric and gate conductor provided at one side of the fin, where the gate conductor is isolated from the channel region by the gate dielectric, wherein the gate conductor extends away from the one side of the fin in a direction parallel to the main surface of the SOI substrate. The semiconductor device has an improved short channel effect and a reduced parasitic capacitance and resistance, which contributes to an improved electrical property and facilitates scaling down of the transistor.

A new insulation system is provided that contains microspheres. This insulation system can be used to provide insulated panels and clamshells, and to insulate annular spaces around objects used to transfer, store, or transport cryogens and other temperature-sensitive materials. This insulation system provides better performance with reduced maintenance than current insulation systems.

A capacitor comprising: a capacitor body including a plurality of laminated dielectric layers, a plurality of inner electrode layers which are respectively disposed between mutually adjacent ones of the dielectric layers, a first main surface located in a laminated direction of the dielectric layers, and a second main surface opposite to the first main surface; a first outer electrode formed on the first main surface of the capacitor body and electrically connected to the inner electrode layers; a second outer electrode formed on the second main surface of the capacitor body and electrically connected to the inner electrode layers; a first dummy electrode formed on the first main surface of the capacitor body; and a second dummy electrode formed on the second main surface of the capacitor body.

A device for epitaxially growing objects of for instance SiC by Chemical Vapor Deposition on a substrate has a first conduit (24) arranged to conduct substantially only a carrier gas to a room (18) receiving the substrate and a second conduit (25) received in the first conduit, having a smaller cross-section than the first conduit and extending in the longitudinal direction of the first conduit with a circumferential space separating it from inner walls of the first conduit. The second conduit is adapted to conduct substantially the entire flow of reactive gases and it ends as seen in the direction of the flows, and emerges into the first conduit at a distance from said room.

A bias generation method or apparatus defined by any one or any practical combination of numerous features that contribute to low noise and/or high efficiency biasing, including: having a charge pump control clock output with a waveform having limited harmonic content or distortion compared to a sine wave; having a ring oscillator to generating a charge pump clock that includes inverters current limited by cascode devices and achieves substantially rail-to-rail output amplitude; having a differential ring oscillator with optional startup and/or phase locking features to produce two phase outputs suitably matched and in adequate phase opposition; having a ring oscillator of less than five stages generating a charge pump clock; capacitively coupling the clock output(s) to some or all of the charge transfer capacitor switches; biasing an FET, which is capacitively coupled to a drive signal, to a bias voltage via an “active bias resistor” circuit that conducts between output terminals only during portions of a waveform appearing between the terminals, and/or wherein the bias voltage is generated by switching a small capacitance at cycles of said waveform. A charge pump for the bias generation may include a regulating feed back loop including an OTA that is also suitable for other uses, the OTA having a ratio-control input that controls a current mirror ratio in a differential amplifier over a continuous range, and optionally has differential outputs including an inverting output produced by a second differential amplifier that optionally includes a variable ratio current mirror controlled by the same ratio-control input. The ratio-control input may therefore control a common mode voltage of the differential outputs of the OTA. A control loop around the OTA may be configured to control the ratio of one or more variable ratio current mirrors, which may particularly control the output common mode voltage, and may control it such that the inverting output level tracks the non-inverting output level to cause the amplifier to function as a high-gain integrator.

An electrical circuit for providing electrical power for use in powering electronic devices, such as monitors, televisions, white goods, data centers, and telecom circuit boards, is described herein. The electrical circuit includes a voltage reduction circuit cell that includes a first capacitor, a second capacitor, a switching circuit, and a hold capacitor. The switching circuit includes a plurality of switching devices that are coupled to the first and the second capacitors for delivering power from an input terminal to an output terminal. The plurality of switching devices includes at least two switching devices that are coupled to ground. The voltage reduction circuit cell also includes a controller for operating the switching circuit in a plurality of operational modes to deliver an output power signal at a desired voltage level.

A system and method for forming a novel C4 solder bump for BLM (Ball Limiting Metallurgy) includes a novel damascene technique is implemented to eliminate the Cu undercut problem and improve the C4 pitch. In the process, a barrier layer metal stack is deposited above a metal pad layer. A top layer of the barrier layer metals (e.g., Cu) is patterned by CMP. Only bottom layers of the barrier metal stack are patterned by a wet etching. The wet etch time for the Cu-based metals is greatly reduced resulting in a reduced undercut. This allows the pitch of the C4 solder bumps to be reduced. An alternate method includes use of multiple vias at the solder bump terminal.

A voltage converter including a transformer having a primary winding connected in series with a switch for cutting-up a supply voltage and having a secondary winding associated with a capacitor providing a D.C. low voltage, and a self-oscillating control circuit of the switch for detecting the end of the demagnetization of an auxiliary winding of the transformer, to turn the switch on, and for detecting the current in the on-state switch to turn it off when this current reaches a reference point. The reference point is made variable according to the voltage across the auxiliary winding.

A non-insulated DC-DC converter a power MOS·FRT for a highside switch and a power MOS·FET for a lowside switch. In the non-insulated DC-DC converter, the power MOS·FET for the highside switch and the power MOS·FET for the lowside switch, driver circuits that control operations of these elements, respectively, and a Schottky barrier diode connected in parallel with the power MOS·FET for the lowside switch are respectively formed in four different semiconductor chips. These four semiconductor chips are housed in one package. The semiconductor chips are mounted over the same die pad. The semiconductor chips are disposed so as to approach each other.

A circuit and method for reducing losses in a DC/DC converter by optimizing gate drive voltage. The circuit and method detect a change in the output load, or more specifically the output current, and adjust the gate voltage accordingly; in other words, providing adaptive gate drive voltage. In response to a reduction of output current, the invention reduces the gate voltage so as to reduce both conduction and switching losses in the semiconductor switching devices in the output stage.

A power supply includes a non-isolated DC-DC converter for use in a power source system having a high side switch and a low side switch, in which HEMT or HFET or gallium nitride device with low capacity and low on-resistance is used for the high side switch and a vertical power MOSFET of silicon device with low on-resistance is used for the low side switch.

A manufacturing method of a semiconductor device includes: forming multiple trenches on a semiconductor substrate; forming a second conductive type semiconductor film in each trench to provide a first column with the substrate between two trenches and a second column with the second conductive type semiconductor film in the trench, the first and second columns alternately repeated along with a predetermined direction; thinning a second side of the substrate; and increasing an impurity concentration in a thinned second side so that a first conductive type layer is provided. The impurity concentration of the first conductive type layer is higher than the first column. The first column provides a drift layer so that a vertical type first-conductive-type channel transistor is formed.

The present invention provides a dicing die bond film in which peeling electrification hardly occurs and which has good tackiness and workability. The dicing die bond film of the present invention is a dicing die bond film including a dicing film and a thermosetting type die bond film provided thereon, wherein the thermosetting type die bond film contains conductive particles, the volume resistivity of the thermosetting type die bond film is 1×10⁻⁶ Ω·cm or more and 1×10⁻³ Ω·cm or less, and the tensile storage modulus of the thermosetting type die bond film at −20° C. before thermal curing is 0.1 to 10 GPa.

A document handling apparatus having a document transport path for moving a document therethrough. A single detector proximate the transport detects a misfeed indication in the transport path. A processing system processes the indication and issues a termination signal if a misfeed is determined.

The embodiments of the present invention include a bias circuit for a power-amplifying device, which receives and amplifies an input RF signal having a series of RF cycles within a modulation envelop. The bias circuit compensates odd-order distortion processes by detecting the power in the input signal and providing a dynamic adjustment to a bias stimulus for the power-amplifying device within a time scale of the modulation envelope.

A projector for image projection, includes: an optical element included by an optical system to project an image; a tripod that supports the projector; and a tripod-fixing part that is connected with the optical element and fixes the tripod, wherein the tripod and tripod-fixing part are each constituted by a heat-conductive member.

The invention provides a keeping warm flocculus which is prepared from raw material by weight including 56%-85% fine denier fibre and/or super fine denier fibre, 0-30% hollow fibre, 5-30% felt fibre. The preparing method includes steps as follows: loosing and mixing various fibre raw material; then combing, lapping for forming fibre net; then processing disorder drafting to the felt net for forming solid net shape crossing struture; then heating and baking the felt net, at least melting surface of the felt fibre for felting surrounding fibre. The fine denier fibre can increase content of still air in the keeping warm flocculus, reduce heat quantity conduction, and can divide space in the keeping warm flocculus into smaller space for avoiding or reducing air convection, accordingly increase warm keeping property of the keeping warm flocculus; the hollow fibre can increase filling power and compress rebound property of the warm keeping flocculus; filling power and compress rebound property of the warm keeping flocculus are increased after being disorder draft.